diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2011-03-07 09:00:06 -0500 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2011-03-09 19:04:02 -0500 |
commit | 41f3863bb050ba881aac6cc7be28fc0602cb629a (patch) | |
tree | 5d931a34d987ed9aec77396465ff1345a36c51e4 /arch/powerpc/sysdev | |
parent | 94347cb34983f9862477776d0c169607c4434f2b (diff) |
powerpc: sysdev/mv64x60_pic irq_data conversion.
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev')
-rw-r--r-- | arch/powerpc/sysdev/mv64x60_pic.c | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c index 485b92477d7c..bc61ebb8987c 100644 --- a/arch/powerpc/sysdev/mv64x60_pic.c +++ b/arch/powerpc/sysdev/mv64x60_pic.c | |||
@@ -76,9 +76,9 @@ static struct irq_host *mv64x60_irq_host; | |||
76 | * mv64x60_chip_low functions | 76 | * mv64x60_chip_low functions |
77 | */ | 77 | */ |
78 | 78 | ||
79 | static void mv64x60_mask_low(unsigned int virq) | 79 | static void mv64x60_mask_low(struct irq_data *d) |
80 | { | 80 | { |
81 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 81 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
82 | unsigned long flags; | 82 | unsigned long flags; |
83 | 83 | ||
84 | spin_lock_irqsave(&mv64x60_lock, flags); | 84 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -89,9 +89,9 @@ static void mv64x60_mask_low(unsigned int virq) | |||
89 | (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO); | 89 | (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO); |
90 | } | 90 | } |
91 | 91 | ||
92 | static void mv64x60_unmask_low(unsigned int virq) | 92 | static void mv64x60_unmask_low(struct irq_data *d) |
93 | { | 93 | { |
94 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 94 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
95 | unsigned long flags; | 95 | unsigned long flags; |
96 | 96 | ||
97 | spin_lock_irqsave(&mv64x60_lock, flags); | 97 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -104,18 +104,18 @@ static void mv64x60_unmask_low(unsigned int virq) | |||
104 | 104 | ||
105 | static struct irq_chip mv64x60_chip_low = { | 105 | static struct irq_chip mv64x60_chip_low = { |
106 | .name = "mv64x60_low", | 106 | .name = "mv64x60_low", |
107 | .mask = mv64x60_mask_low, | 107 | .irq_mask = mv64x60_mask_low, |
108 | .mask_ack = mv64x60_mask_low, | 108 | .irq_mask_ack = mv64x60_mask_low, |
109 | .unmask = mv64x60_unmask_low, | 109 | .irq_unmask = mv64x60_unmask_low, |
110 | }; | 110 | }; |
111 | 111 | ||
112 | /* | 112 | /* |
113 | * mv64x60_chip_high functions | 113 | * mv64x60_chip_high functions |
114 | */ | 114 | */ |
115 | 115 | ||
116 | static void mv64x60_mask_high(unsigned int virq) | 116 | static void mv64x60_mask_high(struct irq_data *d) |
117 | { | 117 | { |
118 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 118 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
119 | unsigned long flags; | 119 | unsigned long flags; |
120 | 120 | ||
121 | spin_lock_irqsave(&mv64x60_lock, flags); | 121 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -126,9 +126,9 @@ static void mv64x60_mask_high(unsigned int virq) | |||
126 | (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI); | 126 | (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI); |
127 | } | 127 | } |
128 | 128 | ||
129 | static void mv64x60_unmask_high(unsigned int virq) | 129 | static void mv64x60_unmask_high(struct irq_data *d) |
130 | { | 130 | { |
131 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 131 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
132 | unsigned long flags; | 132 | unsigned long flags; |
133 | 133 | ||
134 | spin_lock_irqsave(&mv64x60_lock, flags); | 134 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -141,18 +141,18 @@ static void mv64x60_unmask_high(unsigned int virq) | |||
141 | 141 | ||
142 | static struct irq_chip mv64x60_chip_high = { | 142 | static struct irq_chip mv64x60_chip_high = { |
143 | .name = "mv64x60_high", | 143 | .name = "mv64x60_high", |
144 | .mask = mv64x60_mask_high, | 144 | .irq_mask = mv64x60_mask_high, |
145 | .mask_ack = mv64x60_mask_high, | 145 | .irq_mask_ack = mv64x60_mask_high, |
146 | .unmask = mv64x60_unmask_high, | 146 | .irq_unmask = mv64x60_unmask_high, |
147 | }; | 147 | }; |
148 | 148 | ||
149 | /* | 149 | /* |
150 | * mv64x60_chip_gpp functions | 150 | * mv64x60_chip_gpp functions |
151 | */ | 151 | */ |
152 | 152 | ||
153 | static void mv64x60_mask_gpp(unsigned int virq) | 153 | static void mv64x60_mask_gpp(struct irq_data *d) |
154 | { | 154 | { |
155 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 155 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
156 | unsigned long flags; | 156 | unsigned long flags; |
157 | 157 | ||
158 | spin_lock_irqsave(&mv64x60_lock, flags); | 158 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -163,9 +163,9 @@ static void mv64x60_mask_gpp(unsigned int virq) | |||
163 | (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK); | 163 | (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK); |
164 | } | 164 | } |
165 | 165 | ||
166 | static void mv64x60_mask_ack_gpp(unsigned int virq) | 166 | static void mv64x60_mask_ack_gpp(struct irq_data *d) |
167 | { | 167 | { |
168 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 168 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
169 | unsigned long flags; | 169 | unsigned long flags; |
170 | 170 | ||
171 | spin_lock_irqsave(&mv64x60_lock, flags); | 171 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -178,9 +178,9 @@ static void mv64x60_mask_ack_gpp(unsigned int virq) | |||
178 | (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE); | 178 | (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE); |
179 | } | 179 | } |
180 | 180 | ||
181 | static void mv64x60_unmask_gpp(unsigned int virq) | 181 | static void mv64x60_unmask_gpp(struct irq_data *d) |
182 | { | 182 | { |
183 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 183 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
184 | unsigned long flags; | 184 | unsigned long flags; |
185 | 185 | ||
186 | spin_lock_irqsave(&mv64x60_lock, flags); | 186 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -193,9 +193,9 @@ static void mv64x60_unmask_gpp(unsigned int virq) | |||
193 | 193 | ||
194 | static struct irq_chip mv64x60_chip_gpp = { | 194 | static struct irq_chip mv64x60_chip_gpp = { |
195 | .name = "mv64x60_gpp", | 195 | .name = "mv64x60_gpp", |
196 | .mask = mv64x60_mask_gpp, | 196 | .irq_mask = mv64x60_mask_gpp, |
197 | .mask_ack = mv64x60_mask_ack_gpp, | 197 | .irq_mask_ack = mv64x60_mask_ack_gpp, |
198 | .unmask = mv64x60_unmask_gpp, | 198 | .irq_unmask = mv64x60_unmask_gpp, |
199 | }; | 199 | }; |
200 | 200 | ||
201 | /* | 201 | /* |