[POWERPC] 4xx: Add 460EX PCIe support to 4xx pci driver

All this code is needed to properly initialize the 460EX PCIe host
bridge(s). We re-initialize all ports again, even though this has been done
in the bootloader (U-Boot) before. This way we make sure, that we always
run the latest init code in Linux and don't depend on code versions from
U-Boot.

Unfortunately all IBM/AMCC chips currently supported in this PCIe driver need
a different reset-/init-sequence.

Tested on AMCC Canyonlands eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

1 files changed, 59 insertions, 0 deletions

diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index 1c07908dc6ef..d04e40b306fb 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -271,6 +271,59 @@
 #define PESDR1_405EX_PHYSTA             0x044C
 
 /*
+ * 460EX additional DCRs
+ */
+#define PESDR0_460EX_L0BIST             0x0308
+#define PESDR0_460EX_L0BISTSTS          0x0309
+#define PESDR0_460EX_L0CDRCTL           0x030A
+#define PESDR0_460EX_L0DRV              0x030B
+#define PESDR0_460EX_L0REC              0x030C
+#define PESDR0_460EX_L0LPB              0x030D
+#define PESDR0_460EX_L0CLK              0x030E
+#define PESDR0_460EX_PHY_CTL_RST        0x030F
+#define PESDR0_460EX_RSTSTA             0x0310
+#define PESDR0_460EX_OBS                0x0311
+#define PESDR0_460EX_L0ERRC             0x0320
+
+#define PESDR1_460EX_L0BIST             0x0348
+#define PESDR1_460EX_L1BIST             0x0349
+#define PESDR1_460EX_L2BIST             0x034A
+#define PESDR1_460EX_L3BIST             0x034B
+#define PESDR1_460EX_L0BISTSTS          0x034C
+#define PESDR1_460EX_L1BISTSTS          0x034D
+#define PESDR1_460EX_L2BISTSTS          0x034E
+#define PESDR1_460EX_L3BISTSTS          0x034F
+#define PESDR1_460EX_L0CDRCTL           0x0350
+#define PESDR1_460EX_L1CDRCTL           0x0351
+#define PESDR1_460EX_L2CDRCTL           0x0352
+#define PESDR1_460EX_L3CDRCTL           0x0353
+#define PESDR1_460EX_L0DRV              0x0354
+#define PESDR1_460EX_L1DRV              0x0355
+#define PESDR1_460EX_L2DRV              0x0356
+#define PESDR1_460EX_L3DRV              0x0357
+#define PESDR1_460EX_L0REC              0x0358
+#define PESDR1_460EX_L1REC              0x0359
+#define PESDR1_460EX_L2REC              0x035A
+#define PESDR1_460EX_L3REC              0x035B
+#define PESDR1_460EX_L0LPB              0x035C
+#define PESDR1_460EX_L1LPB              0x035D
+#define PESDR1_460EX_L2LPB              0x035E
+#define PESDR1_460EX_L3LPB              0x035F
+#define PESDR1_460EX_L0CLK              0x0360
+#define PESDR1_460EX_L1CLK              0x0361
+#define PESDR1_460EX_L2CLK              0x0362
+#define PESDR1_460EX_L3CLK              0x0363
+#define PESDR1_460EX_PHY_CTL_RST        0x0364
+#define PESDR1_460EX_RSTSTA             0x0365
+#define PESDR1_460EX_OBS                0x0366
+#define PESDR1_460EX_L0ERRC             0x0368
+#define PESDR1_460EX_L1ERRC             0x0369
+#define PESDR1_460EX_L2ERRC             0x036A
+#define PESDR1_460EX_L3ERRC             0x036B
+#define PESDR0_460EX_IHS1               0x036C
+#define PESDR0_460EX_IHS2               0x036D
+
+/*
  * Of the above, some are common offsets from the base
  */
 #define PESDRn_UTLSET1                  0x00
@@ -353,6 +406,12 @@
 #define PECFG_POM2LAL           0x390
 #define PECFG_POM2LAH           0x394
 
+/* SDR Bit Mappings */
+#define PESDRx_RCSSET_HLDPLB    0x10000000
+#define PESDRx_RCSSET_RSTGU     0x01000000
+#define PESDRx_RCSSET_RDY       0x00100000
+#define PESDRx_RCSSET_RSTDL     0x00010000
+#define PESDRx_RCSSET_RSTPYN    0x00001000
 
 enum
 {