powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx

Adds a register to the config space for the 460sx.  Changes the vc0
detect to a pll detect.  maps configuration space to test the link
status.  changes the setup to enable gen2 devices to operate at gen2
speeds.  fixes mapping that was not correct for the 460sx.  added
bit definitions for the OMRxMSKL registers.  Removed reserved bit
that was set incorrectly in the OMR2MSKL register.

tested on the 460sx eiger and custom board

Signed-off-by: Ayman El-Khashab <ayman@elkhashab.com>
Signed-off-by: Josh Boyer <jwboyer@gmail.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index c39a134e8684..32ce763a375a 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -464,6 +464,18 @@
 #define PECFG_POM2LAL           0x390
 #define PECFG_POM2LAH           0x394
 
+/* 460sx only */
+#define PECFG_460SX_DLLSTA     0x3f8
+
+/* 460sx Bit Mappings */
+#define PECFG_460SX_DLLSTA_LINKUP        0x00000010
+#define DCRO_PEGPL_460SX_OMR1MSKL_UOT    0x00000004
+
+/* PEGPL Bit Mappings */
+#define DCRO_PEGPL_OMRxMSKL_VAL  0x00000001
+#define DCRO_PEGPL_OMR1MSKL_UOT  0x00000002
+#define DCRO_PEGPL_OMR3MSKL_IO   0x00000002
+
 /* SDR Bit Mappings */
 #define PESDRx_RCSSET_HLDPLB    0x10000000
 #define PESDRx_RCSSET_RSTGU     0x01000000