diff options
author | Valentine Barshak <vbarshak@ru.mvista.com> | 2008-03-06 09:34:52 -0500 |
---|---|---|
committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2008-03-26 08:23:09 -0400 |
commit | 6e42b21bb91a562cd843a156586fe7b5954f58b3 (patch) | |
tree | ae19531d4221350b0162a138109d35172ddca1ec /arch/powerpc/sysdev/ppc4xx_pci.c | |
parent | 266d028acb615e1766c3fb9530c9e86de8476a33 (diff) |
[POWERPC] 4xx: Use dcri_clrset() for PCIe indirect dcr read/modify/write access
Use dcri_clrset() for PCIe SDR0 read/modify/write access.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/sysdev/ppc4xx_pci.c')
-rw-r--r-- | arch/powerpc/sysdev/ppc4xx_pci.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index d183b8390ec3..6c925b7975f9 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c | |||
@@ -646,7 +646,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np) | |||
646 | int time_out = 20; | 646 | int time_out = 20; |
647 | 647 | ||
648 | /* Set PLL clock receiver to LVPECL */ | 648 | /* Set PLL clock receiver to LVPECL */ |
649 | mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28); | 649 | dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); |
650 | 650 | ||
651 | /* Shouldn't we do all the calibration stuff etc... here ? */ | 651 | /* Shouldn't we do all the calibration stuff etc... here ? */ |
652 | if (ppc440spe_pciex_check_reset(np)) | 652 | if (ppc440spe_pciex_check_reset(np)) |
@@ -660,8 +660,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np) | |||
660 | } | 660 | } |
661 | 661 | ||
662 | /* De-assert reset of PCIe PLL, wait for lock */ | 662 | /* De-assert reset of PCIe PLL, wait for lock */ |
663 | mtdcri(SDR0, PESDR0_PLLLCT1, | 663 | dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); |
664 | mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24)); | ||
665 | udelay(3); | 664 | udelay(3); |
666 | 665 | ||
667 | while (time_out) { | 666 | while (time_out) { |
@@ -713,9 +712,8 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |||
713 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, | 712 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, |
714 | 0x35000000); | 713 | 0x35000000); |
715 | } | 714 | } |
716 | val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET); | 715 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, |
717 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, | 716 | (1 << 24) | (1 << 16), 1 << 12); |
718 | (val & ~(1 << 24 | 1 << 16)) | 1 << 12); | ||
719 | 717 | ||
720 | return 0; | 718 | return 0; |
721 | } | 719 | } |
@@ -1156,8 +1154,7 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) | |||
1156 | port->link = 0; | 1154 | port->link = 0; |
1157 | } | 1155 | } |
1158 | 1156 | ||
1159 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, | 1157 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); |
1160 | mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20); | ||
1161 | msleep(100); | 1158 | msleep(100); |
1162 | 1159 | ||
1163 | return 0; | 1160 | return 0; |