diff options
author | Tirumala Marri <tmarri@amcc.com> | 2009-12-21 17:49:41 -0500 |
---|---|---|
committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2010-05-07 15:07:19 -0400 |
commit | e2efc09e52680cecb0ca624e379cb4b4c56157c3 (patch) | |
tree | b32c902a33371e88aea9b62d4159bfa4998a12c6 /arch/powerpc/sysdev/ppc4xx_pci.c | |
parent | 1ed31d6db90d51010545921e59d369d2f92b7ac2 (diff) |
powerpc/44x: Adding PCI-E support for PowerPC 460SX based SOC.
Add support for PCI-e on the AMCC 460SX boards
Signed-off-by: Tirumala Marri <tmarri@amcc.com>
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/sysdev/ppc4xx_pci.c')
-rw-r--r-- | arch/powerpc/sysdev/ppc4xx_pci.c | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index 106d767bf65b..156aa7d36258 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c | |||
@@ -974,6 +974,123 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata = | |||
974 | .setup_utl = ppc460ex_pciex_init_utl, | 974 | .setup_utl = ppc460ex_pciex_init_utl, |
975 | }; | 975 | }; |
976 | 976 | ||
977 | static int __init ppc460sx_pciex_core_init(struct device_node *np) | ||
978 | { | ||
979 | /* HSS drive amplitude */ | ||
980 | mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211); | ||
981 | mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211); | ||
982 | mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211); | ||
983 | mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211); | ||
984 | mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211); | ||
985 | mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211); | ||
986 | mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211); | ||
987 | mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211); | ||
988 | |||
989 | mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211); | ||
990 | mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211); | ||
991 | mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211); | ||
992 | mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211); | ||
993 | |||
994 | mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211); | ||
995 | mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211); | ||
996 | mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211); | ||
997 | mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211); | ||
998 | |||
999 | /* HSS TX pre-emphasis */ | ||
1000 | mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987); | ||
1001 | mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987); | ||
1002 | mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987); | ||
1003 | mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987); | ||
1004 | mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987); | ||
1005 | mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987); | ||
1006 | mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987); | ||
1007 | mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987); | ||
1008 | |||
1009 | mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987); | ||
1010 | mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987); | ||
1011 | mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987); | ||
1012 | mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987); | ||
1013 | |||
1014 | mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987); | ||
1015 | mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987); | ||
1016 | mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987); | ||
1017 | mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987); | ||
1018 | |||
1019 | /* HSS TX calibration control */ | ||
1020 | mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222); | ||
1021 | mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000); | ||
1022 | mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000); | ||
1023 | |||
1024 | /* HSS TX slew control */ | ||
1025 | mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF); | ||
1026 | mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000); | ||
1027 | mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000); | ||
1028 | |||
1029 | udelay(100); | ||
1030 | |||
1031 | /* De-assert PLLRESET */ | ||
1032 | dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0); | ||
1033 | |||
1034 | /* Reset DL, UTL, GPL before configuration */ | ||
1035 | mtdcri(SDR0, PESDR0_460SX_RCSSET, | ||
1036 | PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); | ||
1037 | mtdcri(SDR0, PESDR1_460SX_RCSSET, | ||
1038 | PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); | ||
1039 | mtdcri(SDR0, PESDR2_460SX_RCSSET, | ||
1040 | PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU); | ||
1041 | |||
1042 | udelay(100); | ||
1043 | |||
1044 | /* | ||
1045 | * If bifurcation is not enabled, u-boot would have disabled the | ||
1046 | * third PCIe port | ||
1047 | */ | ||
1048 | if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) == | ||
1049 | 0x00000001)) { | ||
1050 | printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n"); | ||
1051 | printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n"); | ||
1052 | return 3; | ||
1053 | } | ||
1054 | |||
1055 | printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n"); | ||
1056 | return 2; | ||
1057 | } | ||
1058 | |||
1059 | static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | ||
1060 | { | ||
1061 | |||
1062 | if (port->endpoint) | ||
1063 | dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, | ||
1064 | 0x01000000, 0); | ||
1065 | else | ||
1066 | dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, | ||
1067 | 0, 0x01000000); | ||
1068 | |||
1069 | /*Gen-1*/ | ||
1070 | mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000); | ||
1071 | |||
1072 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, | ||
1073 | (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL), | ||
1074 | PESDRx_RCSSET_RSTPYN); | ||
1075 | |||
1076 | port->has_ibpre = 1; | ||
1077 | |||
1078 | return 0; | ||
1079 | } | ||
1080 | |||
1081 | static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port) | ||
1082 | { | ||
1083 | /* Max 128 Bytes */ | ||
1084 | out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); | ||
1085 | return 0; | ||
1086 | } | ||
1087 | |||
1088 | static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = { | ||
1089 | .core_init = ppc460sx_pciex_core_init, | ||
1090 | .port_init_hw = ppc460sx_pciex_init_port_hw, | ||
1091 | .setup_utl = ppc460sx_pciex_init_utl, | ||
1092 | }; | ||
1093 | |||
977 | #endif /* CONFIG_44x */ | 1094 | #endif /* CONFIG_44x */ |
978 | 1095 | ||
979 | #ifdef CONFIG_40x | 1096 | #ifdef CONFIG_40x |
@@ -1089,6 +1206,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np) | |||
1089 | } | 1206 | } |
1090 | if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) | 1207 | if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) |
1091 | ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops; | 1208 | ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops; |
1209 | if (of_device_is_compatible(np, "ibm,plb-pciex-460sx")) | ||
1210 | ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops; | ||
1092 | #endif /* CONFIG_44x */ | 1211 | #endif /* CONFIG_44x */ |
1093 | #ifdef CONFIG_40x | 1212 | #ifdef CONFIG_40x |
1094 | if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) | 1213 | if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) |