diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-23 12:22:16 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-24 13:27:32 -0500 |
commit | 8a327f23e23fa509e6e3c2263ae1cc0a67dec387 (patch) | |
tree | 119abf09e1ec9babaf78e6889187f9d54864b118 /arch/powerpc/sysdev/mpic.c | |
parent | 5a9a8d1a99c617df82339456fbdd30d6ed3a856b (diff) | |
parent | d315777b32a4696feb86f2a0c9e9f39c94683649 (diff) |
Merge remote branch 'linus/master' into drm-intel-fixes
Merge with Linus to resolve conflicting fixes for the reusing the stale
HEAD value during intel_ring_wait().
Conflicts:
drivers/gpu/drm/i915/intel_ringbuffer.c
Diffstat (limited to 'arch/powerpc/sysdev/mpic.c')
-rw-r--r-- | arch/powerpc/sysdev/mpic.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 7c1342618a30..b0c8469e5ddd 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c | |||
@@ -674,7 +674,8 @@ void mpic_unmask_irq(unsigned int irq) | |||
674 | /* make sure mask gets to controller before we return to user */ | 674 | /* make sure mask gets to controller before we return to user */ |
675 | do { | 675 | do { |
676 | if (!loops--) { | 676 | if (!loops--) { |
677 | printk(KERN_ERR "mpic_enable_irq timeout\n"); | 677 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
678 | __func__, src); | ||
678 | break; | 679 | break; |
679 | } | 680 | } |
680 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); | 681 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
@@ -695,7 +696,8 @@ void mpic_mask_irq(unsigned int irq) | |||
695 | /* make sure mask gets to controller before we return to user */ | 696 | /* make sure mask gets to controller before we return to user */ |
696 | do { | 697 | do { |
697 | if (!loops--) { | 698 | if (!loops--) { |
698 | printk(KERN_ERR "mpic_enable_irq timeout\n"); | 699 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
700 | __func__, src); | ||
699 | break; | 701 | break; |
700 | } | 702 | } |
701 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); | 703 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |