powerpc/mpic: allow coreint to be determined by MPIC version

This will be used by the qemu-e500 platform, as the MPIC version (and
thus whether we have coreint) depends on how QEMU is configured.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 23 insertions, 3 deletions

diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 66944255520d..d30e6a676c89 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1182,6 +1182,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         const char *vers;
         const u32 *psrc;
         u32 last_irq;
+        u32 fsl_version = 0;
 
         /* Default MPIC search parameters */
         static const struct of_device_id __initconst mpic_device_id[] = {
@@ -1314,7 +1315,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
 
         if (mpic->flags & MPIC_FSL) {
-                u32 brr1, version;
+                u32 brr1;
                 int ret;
 
                 /*
@@ -1327,7 +1328,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
 
                 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
                                 MPIC_FSL_BRR1);
-                version = brr1 & MPIC_FSL_BRR1_VER;
+                fsl_version = brr1 & MPIC_FSL_BRR1_VER;
 
                 /* Error interrupt mask register (EIMR) is required for
                  * handling individual device error interrupts. EIMR
@@ -1342,11 +1343,30 @@ struct mpic * __init mpic_alloc(struct device_node *node,
                  * is the number of vectors which have been consumed by
                  * ipis and timer interrupts.
                  */
-                if (version >= 0x401) {
+                if (fsl_version >= 0x401) {
                         ret = mpic_setup_error_int(mpic, intvec_top - 12);
                         if (ret)
                                 return NULL;
                 }
+
+        }
+
+        /*
+         * EPR is only available starting with v4.0.  To support
+         * platforms that don't know the MPIC version at compile-time,
+         * such as qemu-e500, turn off coreint if this MPIC doesn't
+         * support it.  Note that we never enable it if it wasn't
+         * requested in the first place.
+         *
+         * This is done outside the MPIC_FSL check, so that we
+         * also disable coreint if the MPIC node doesn't have
+         * an "fsl,mpic" compatible at all.  This will be the case
+         * with device trees generated by older versions of QEMU.
+         * fsl_version will be zero if MPIC_FSL is not set.
+         */
+        if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) {
+                WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq);
+                ppc_md.get_irq = mpic_get_irq;
         }
 
         /* Reset */