diff options
author | Kumar Gala <galak@gate.crashing.org> | 2005-11-14 13:54:33 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-01-08 22:48:57 -0500 |
commit | 1cd8e506209223ed10da805d99be55e268f4023c (patch) | |
tree | ccec0c8aff4f351baebad5dcc213915c3379ca6e /arch/powerpc/sysdev/ipic.h | |
parent | 3d1229d6ae92ed1994f4411b8493327ef8f4b76f (diff) |
[PATCH] powerpc: moved ipic code to arch/powerpc
Moved 83xx and QUICC Engine interrupt handling code into arch/powerpc
as a precursor of getting 83xx sub-arch building in arch/powerpc.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/sysdev/ipic.h')
-rw-r--r-- | arch/powerpc/sysdev/ipic.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/ipic.h b/arch/powerpc/sysdev/ipic.h new file mode 100644 index 000000000000..a7ce7da8785c --- /dev/null +++ b/arch/powerpc/sysdev/ipic.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * arch/ppc/kernel/ipic.h | ||
3 | * | ||
4 | * IPIC private definitions and structure. | ||
5 | * | ||
6 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
7 | * | ||
8 | * Copyright 2005 Freescale Semiconductor, Inc | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | */ | ||
15 | #ifndef __IPIC_H__ | ||
16 | #define __IPIC_H__ | ||
17 | |||
18 | #include <asm/ipic.h> | ||
19 | |||
20 | #define MPC83xx_IPIC_SIZE (0x00100) | ||
21 | |||
22 | /* System Global Interrupt Configuration Register */ | ||
23 | #define SICFR_IPSA 0x00010000 | ||
24 | #define SICFR_IPSD 0x00080000 | ||
25 | #define SICFR_MPSA 0x00200000 | ||
26 | #define SICFR_MPSB 0x00400000 | ||
27 | |||
28 | /* System External Interrupt Mask Register */ | ||
29 | #define SEMSR_SIRQ0 0x00008000 | ||
30 | |||
31 | /* System Error Control Register */ | ||
32 | #define SERCR_MCPR 0x00000001 | ||
33 | |||
34 | struct ipic { | ||
35 | volatile u32 __iomem *regs; | ||
36 | unsigned int irq_offset; | ||
37 | }; | ||
38 | |||
39 | struct ipic_info { | ||
40 | u8 pend; /* pending register offset from base */ | ||
41 | u8 mask; /* mask register offset from base */ | ||
42 | u8 prio; /* priority register offset from base */ | ||
43 | u8 force; /* force register offset from base */ | ||
44 | u8 bit; /* register bit position (as per doc) | ||
45 | bit mask = 1 << (31 - bit) */ | ||
46 | u8 prio_mask; /* priority mask value */ | ||
47 | }; | ||
48 | |||
49 | #endif /* __IPIC_H__ */ | ||