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authorLi Yang <leoli@freescale.com>2007-10-19 07:38:43 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-12-11 14:57:18 -0500
commitf03ca957faa4d51f3a9c52c1ad5ea61a0978c637 (patch)
tree826d9603580b11a7910e0446c351cbf64e841d81 /arch/powerpc/sysdev/ipic.c
parenta58d52443fca9cc28ed580e3ccfcae3c3d49df33 (diff)
[POWERPC] ipic: add new interrupts introduced by new chip
These interrupts are introduced by the latest Freescale SoC such as MPC837x. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev/ipic.c')
-rw-r--r--arch/powerpc/sysdev/ipic.c138
1 files changed, 133 insertions, 5 deletions
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 05a56e55804c..7168b0349792 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -33,6 +33,30 @@ static struct ipic * primary_ipic;
33static DEFINE_SPINLOCK(ipic_lock); 33static DEFINE_SPINLOCK(ipic_lock);
34 34
35static struct ipic_info ipic_info[] = { 35static struct ipic_info ipic_info[] = {
36 [1] = {
37 .pend = IPIC_SIPNR_H,
38 .mask = IPIC_SIMSR_H,
39 .prio = IPIC_SIPRR_C,
40 .force = IPIC_SIFCR_H,
41 .bit = 16,
42 .prio_mask = 0,
43 },
44 [2] = {
45 .pend = IPIC_SIPNR_H,
46 .mask = IPIC_SIMSR_H,
47 .prio = IPIC_SIPRR_C,
48 .force = IPIC_SIFCR_H,
49 .bit = 17,
50 .prio_mask = 1,
51 },
52 [4] = {
53 .pend = IPIC_SIPNR_H,
54 .mask = IPIC_SIMSR_H,
55 .prio = IPIC_SIPRR_C,
56 .force = IPIC_SIFCR_H,
57 .bit = 19,
58 .prio_mask = 3,
59 },
36 [9] = { 60 [9] = {
37 .pend = IPIC_SIPNR_H, 61 .pend = IPIC_SIPNR_H,
38 .mask = IPIC_SIMSR_H, 62 .mask = IPIC_SIMSR_H,
@@ -57,6 +81,22 @@ static struct ipic_info ipic_info[] = {
57 .bit = 26, 81 .bit = 26,
58 .prio_mask = 2, 82 .prio_mask = 2,
59 }, 83 },
84 [12] = {
85 .pend = IPIC_SIPNR_H,
86 .mask = IPIC_SIMSR_H,
87 .prio = IPIC_SIPRR_D,
88 .force = IPIC_SIFCR_H,
89 .bit = 27,
90 .prio_mask = 3,
91 },
92 [13] = {
93 .pend = IPIC_SIPNR_H,
94 .mask = IPIC_SIMSR_H,
95 .prio = IPIC_SIPRR_D,
96 .force = IPIC_SIFCR_H,
97 .bit = 28,
98 .prio_mask = 4,
99 },
60 [14] = { 100 [14] = {
61 .pend = IPIC_SIPNR_H, 101 .pend = IPIC_SIPNR_H,
62 .mask = IPIC_SIMSR_H, 102 .mask = IPIC_SIMSR_H,
@@ -201,6 +241,46 @@ static struct ipic_info ipic_info[] = {
201 .bit = 7, 241 .bit = 7,
202 .prio_mask = 7, 242 .prio_mask = 7,
203 }, 243 },
244 [42] = {
245 .pend = IPIC_SIPNR_H,
246 .mask = IPIC_SIMSR_H,
247 .prio = IPIC_SIPRR_B,
248 .force = IPIC_SIFCR_H,
249 .bit = 10,
250 .prio_mask = 2,
251 },
252 [44] = {
253 .pend = IPIC_SIPNR_H,
254 .mask = IPIC_SIMSR_H,
255 .prio = IPIC_SIPRR_B,
256 .force = IPIC_SIFCR_H,
257 .bit = 12,
258 .prio_mask = 4,
259 },
260 [45] = {
261 .pend = IPIC_SIPNR_H,
262 .mask = IPIC_SIMSR_H,
263 .prio = IPIC_SIPRR_B,
264 .force = IPIC_SIFCR_H,
265 .bit = 13,
266 .prio_mask = 5,
267 },
268 [46] = {
269 .pend = IPIC_SIPNR_H,
270 .mask = IPIC_SIMSR_H,
271 .prio = IPIC_SIPRR_B,
272 .force = IPIC_SIFCR_H,
273 .bit = 14,
274 .prio_mask = 6,
275 },
276 [47] = {
277 .pend = IPIC_SIPNR_H,
278 .mask = IPIC_SIMSR_H,
279 .prio = IPIC_SIPRR_B,
280 .force = IPIC_SIFCR_H,
281 .bit = 15,
282 .prio_mask = 7,
283 },
204 [48] = { 284 [48] = {
205 .pend = IPIC_SEPNR, 285 .pend = IPIC_SEPNR,
206 .mask = IPIC_SEMSR, 286 .mask = IPIC_SEMSR,
@@ -336,6 +416,20 @@ static struct ipic_info ipic_info[] = {
336 .force = IPIC_SIFCR_L, 416 .force = IPIC_SIFCR_L,
337 .bit = 16, 417 .bit = 16,
338 }, 418 },
419 [81] = {
420 .pend = IPIC_SIPNR_L,
421 .mask = IPIC_SIMSR_L,
422 .prio = 0,
423 .force = IPIC_SIFCR_L,
424 .bit = 17,
425 },
426 [82] = {
427 .pend = IPIC_SIPNR_L,
428 .mask = IPIC_SIMSR_L,
429 .prio = 0,
430 .force = IPIC_SIFCR_L,
431 .bit = 18,
432 },
339 [84] = { 433 [84] = {
340 .pend = IPIC_SIPNR_L, 434 .pend = IPIC_SIPNR_L,
341 .mask = IPIC_SIMSR_L, 435 .mask = IPIC_SIMSR_L,
@@ -350,6 +444,34 @@ static struct ipic_info ipic_info[] = {
350 .force = IPIC_SIFCR_L, 444 .force = IPIC_SIFCR_L,
351 .bit = 21, 445 .bit = 21,
352 }, 446 },
447 [86] = {
448 .pend = IPIC_SIPNR_L,
449 .mask = IPIC_SIMSR_L,
450 .prio = 0,
451 .force = IPIC_SIFCR_L,
452 .bit = 22,
453 },
454 [87] = {
455 .pend = IPIC_SIPNR_L,
456 .mask = IPIC_SIMSR_L,
457 .prio = 0,
458 .force = IPIC_SIFCR_L,
459 .bit = 23,
460 },
461 [88] = {
462 .pend = IPIC_SIPNR_L,
463 .mask = IPIC_SIMSR_L,
464 .prio = 0,
465 .force = IPIC_SIFCR_L,
466 .bit = 24,
467 },
468 [89] = {
469 .pend = IPIC_SIPNR_L,
470 .mask = IPIC_SIMSR_L,
471 .prio = 0,
472 .force = IPIC_SIFCR_L,
473 .bit = 25,
474 },
353 [90] = { 475 [90] = {
354 .pend = IPIC_SIPNR_L, 476 .pend = IPIC_SIPNR_L,
355 .mask = IPIC_SIMSR_L, 477 .mask = IPIC_SIMSR_L,
@@ -593,6 +715,10 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
593 * configure SICFR accordingly */ 715 * configure SICFR accordingly */
594 if (flags & IPIC_SPREADMODE_GRP_A) 716 if (flags & IPIC_SPREADMODE_GRP_A)
595 temp |= SICFR_IPSA; 717 temp |= SICFR_IPSA;
718 if (flags & IPIC_SPREADMODE_GRP_B)
719 temp |= SICFR_IPSB;
720 if (flags & IPIC_SPREADMODE_GRP_C)
721 temp |= SICFR_IPSC;
596 if (flags & IPIC_SPREADMODE_GRP_D) 722 if (flags & IPIC_SPREADMODE_GRP_D)
597 temp |= SICFR_IPSD; 723 temp |= SICFR_IPSD;
598 if (flags & IPIC_SPREADMODE_MIX_A) 724 if (flags & IPIC_SPREADMODE_MIX_A)
@@ -600,7 +726,7 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
600 if (flags & IPIC_SPREADMODE_MIX_B) 726 if (flags & IPIC_SPREADMODE_MIX_B)
601 temp |= SICFR_MPSB; 727 temp |= SICFR_MPSB;
602 728
603 ipic_write(ipic->regs, IPIC_SICNR, temp); 729 ipic_write(ipic->regs, IPIC_SICFR, temp);
604 730
605 /* handle MCP route */ 731 /* handle MCP route */
606 temp = 0; 732 temp = 0;
@@ -672,10 +798,12 @@ void ipic_set_highest_priority(unsigned int virq)
672 798
673void ipic_set_default_priority(void) 799void ipic_set_default_priority(void)
674{ 800{
675 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_SIPRR_A_DEFAULT); 801 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
676 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_SIPRR_D_DEFAULT); 802 ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
677 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_SMPRR_A_DEFAULT); 803 ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
678 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_SMPRR_B_DEFAULT); 804 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
805 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
806 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
679} 807}
680 808
681void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq) 809void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 05:35:19 -0500