diff options
author | John Rigby <jrigby@freescale.com> | 2008-01-17 19:05:32 -0500 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2008-01-23 20:34:24 -0500 |
commit | a7267d679fc5a2f1d3f3f247e22a9824f17b507a (patch) | |
tree | 92a31efe5fb5c2181161c35b94c59d443c582276 /arch/powerpc/sysdev/ipic.c | |
parent | e3bc3a09bdfc1b3b88b32d7960c4c3b84a2b860f (diff) |
[POWERPC] Add support for mpc512x interrupts to ipic
Added ipic_info entries for vectors used by 512x that
were previously unused by 83xx.
Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev/ipic.c')
-rw-r--r-- | arch/powerpc/sysdev/ipic.c | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index 7274750fd9c6..4c016da68426 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c | |||
@@ -48,6 +48,13 @@ static struct ipic_info ipic_info[] = { | |||
48 | .bit = 17, | 48 | .bit = 17, |
49 | .prio_mask = 1, | 49 | .prio_mask = 1, |
50 | }, | 50 | }, |
51 | [3] = { | ||
52 | .mask = IPIC_SIMSR_H, | ||
53 | .prio = IPIC_SIPRR_C, | ||
54 | .force = IPIC_SIFCR_H, | ||
55 | .bit = 18, | ||
56 | .prio_mask = 2, | ||
57 | }, | ||
51 | [4] = { | 58 | [4] = { |
52 | .mask = IPIC_SIMSR_H, | 59 | .mask = IPIC_SIMSR_H, |
53 | .prio = IPIC_SIPRR_C, | 60 | .prio = IPIC_SIPRR_C, |
@@ -55,6 +62,34 @@ static struct ipic_info ipic_info[] = { | |||
55 | .bit = 19, | 62 | .bit = 19, |
56 | .prio_mask = 3, | 63 | .prio_mask = 3, |
57 | }, | 64 | }, |
65 | [5] = { | ||
66 | .mask = IPIC_SIMSR_H, | ||
67 | .prio = IPIC_SIPRR_C, | ||
68 | .force = IPIC_SIFCR_H, | ||
69 | .bit = 20, | ||
70 | .prio_mask = 4, | ||
71 | }, | ||
72 | [6] = { | ||
73 | .mask = IPIC_SIMSR_H, | ||
74 | .prio = IPIC_SIPRR_C, | ||
75 | .force = IPIC_SIFCR_H, | ||
76 | .bit = 21, | ||
77 | .prio_mask = 5, | ||
78 | }, | ||
79 | [7] = { | ||
80 | .mask = IPIC_SIMSR_H, | ||
81 | .prio = IPIC_SIPRR_C, | ||
82 | .force = IPIC_SIFCR_H, | ||
83 | .bit = 22, | ||
84 | .prio_mask = 6, | ||
85 | }, | ||
86 | [8] = { | ||
87 | .mask = IPIC_SIMSR_H, | ||
88 | .prio = IPIC_SIPRR_C, | ||
89 | .force = IPIC_SIFCR_H, | ||
90 | .bit = 23, | ||
91 | .prio_mask = 7, | ||
92 | }, | ||
58 | [9] = { | 93 | [9] = { |
59 | .mask = IPIC_SIMSR_H, | 94 | .mask = IPIC_SIMSR_H, |
60 | .prio = IPIC_SIPRR_D, | 95 | .prio = IPIC_SIPRR_D, |
@@ -223,6 +258,20 @@ static struct ipic_info ipic_info[] = { | |||
223 | .bit = 7, | 258 | .bit = 7, |
224 | .prio_mask = 7, | 259 | .prio_mask = 7, |
225 | }, | 260 | }, |
261 | [40] = { | ||
262 | .mask = IPIC_SIMSR_H, | ||
263 | .prio = IPIC_SIPRR_B, | ||
264 | .force = IPIC_SIFCR_H, | ||
265 | .bit = 8, | ||
266 | .prio_mask = 0, | ||
267 | }, | ||
268 | [41] = { | ||
269 | .mask = IPIC_SIMSR_H, | ||
270 | .prio = IPIC_SIPRR_B, | ||
271 | .force = IPIC_SIFCR_H, | ||
272 | .bit = 9, | ||
273 | .prio_mask = 1, | ||
274 | }, | ||
226 | [42] = { | 275 | [42] = { |
227 | .mask = IPIC_SIMSR_H, | 276 | .mask = IPIC_SIMSR_H, |
228 | .prio = IPIC_SIPRR_B, | 277 | .prio = IPIC_SIPRR_B, |
@@ -230,6 +279,13 @@ static struct ipic_info ipic_info[] = { | |||
230 | .bit = 10, | 279 | .bit = 10, |
231 | .prio_mask = 2, | 280 | .prio_mask = 2, |
232 | }, | 281 | }, |
282 | [43] = { | ||
283 | .mask = IPIC_SIMSR_H, | ||
284 | .prio = IPIC_SIPRR_B, | ||
285 | .force = IPIC_SIFCR_H, | ||
286 | .bit = 11, | ||
287 | .prio_mask = 3, | ||
288 | }, | ||
233 | [44] = { | 289 | [44] = { |
234 | .mask = IPIC_SIMSR_H, | 290 | .mask = IPIC_SIMSR_H, |
235 | .prio = IPIC_SIPRR_B, | 291 | .prio = IPIC_SIPRR_B, |
@@ -387,6 +443,12 @@ static struct ipic_info ipic_info[] = { | |||
387 | .force = IPIC_SIFCR_L, | 443 | .force = IPIC_SIFCR_L, |
388 | .bit = 18, | 444 | .bit = 18, |
389 | }, | 445 | }, |
446 | [83] = { | ||
447 | .mask = IPIC_SIMSR_L, | ||
448 | .prio = 0, | ||
449 | .force = IPIC_SIFCR_L, | ||
450 | .bit = 19, | ||
451 | }, | ||
390 | [84] = { | 452 | [84] = { |
391 | .mask = IPIC_SIMSR_L, | 453 | .mask = IPIC_SIMSR_L, |
392 | .prio = 0, | 454 | .prio = 0, |