[POWERPC] 86xx: Workaround PCI_PRIMARY_BUS usage

The Freescale PCI-e controllers have an issue in that they use the
PCI_PRIMARY_BUS register in the virtual P2P bridge to determine which
bus number to match on when generating a type 0 config cycle.  The
issue is if we are renumbering bus numbers to match Linux we will try
setting the PCI_PRIMARY_BUS and will not know which bus number to use
for generating type 0 config cycles.  We surpress writing the register
in the P2P bridge and always keep it at zero.

In the future when proper PCI domain support is working we should be
able to remove this.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index 3a1612253c60..c7e6e859b393 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -103,6 +103,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
                  (0x80000000 | (bus_no << 16)
                   | (devfn << 8) | reg | cfg_type));
 
+        /* surpress setting of PCI_PRIMARY_BUS */
+        if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
+                if ((offset == PCI_PRIMARY_BUS) &&
+                        (bus->number == hose->first_busno))
+                val &= 0xffffff00;
+
         /*
          * Note: the caller has already checked that offset is
          * suitably aligned and that len is 1, 2 or 4.