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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-05-05 23:40:40 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-05-05 23:40:40 -0400
commit3fd47f063b17692e843128e2abda3e697df42198 (patch)
treed90a5bdd247b0cc5af7cf78cd18cf6e27a884f00 /arch/powerpc/sysdev/fsl_pci.c
parent342d6666f7276723e418b91c885b0c03f02eeaaf (diff)
powerpc/pci: Support per-aperture memory offset
The PCI core supports an offset per aperture nowadays but our arch code still has a single offset per host bridge representing the difference betwen CPU memory addresses and PCI MMIO addresses. This is a problem as new machines and hypervisor versions are coming out where the 64-bit windows will have a different offset (basically mapped 1:1) from the 32-bit windows. This fixes it by using separate offsets. In the long run, we probably want to get rid of that intermediary struct pci_controller and have those directly stored into the pci_host_bridge as they are parsed but this will be a more invasive change. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.c')
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index cffe7edac858..028ac1f71b51 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -178,7 +178,7 @@ static void setup_pci_atmu(struct pci_controller *hose)
178 struct ccsr_pci __iomem *pci = hose->private_data; 178 struct ccsr_pci __iomem *pci = hose->private_data;
179 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 179 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
180 u64 mem, sz, paddr_hi = 0; 180 u64 mem, sz, paddr_hi = 0;
181 u64 paddr_lo = ULLONG_MAX; 181 u64 offset = 0, paddr_lo = ULLONG_MAX;
182 u32 pcicsrbar = 0, pcicsrbar_sz; 182 u32 pcicsrbar = 0, pcicsrbar_sz;
183 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 183 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
184 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 184 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
@@ -208,8 +208,9 @@ static void setup_pci_atmu(struct pci_controller *hose)
208 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 208 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
209 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 209 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
210 210
211 n = setup_one_atmu(pci, j, &hose->mem_resources[i], 211 /* We assume all memory resources have the same offset */
212 hose->pci_mem_offset); 212 offset = hose->mem_offset[i];
213 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
213 214
214 if (n < 0 || j >= 5) { 215 if (n < 0 || j >= 5) {
215 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 216 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
@@ -239,8 +240,8 @@ static void setup_pci_atmu(struct pci_controller *hose)
239 } 240 }
240 241
241 /* convert to pci address space */ 242 /* convert to pci address space */
242 paddr_hi -= hose->pci_mem_offset; 243 paddr_hi -= offset;
243 paddr_lo -= hose->pci_mem_offset; 244 paddr_lo -= offset;
244 245
245 if (paddr_hi == paddr_lo) { 246 if (paddr_hi == paddr_lo) {
246 pr_err("%s: No outbound window space\n", name); 247 pr_err("%s: No outbound window space\n", name);