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authorGerlando Falauto <gerlando.falauto@keymile.com>2012-12-07 10:09:14 -0500
committerKumar Gala <galak@kernel.crashing.org>2013-02-13 08:49:06 -0500
commit14f40f31e8ffd639c2e3e0cd90ec6dd8b536144b (patch)
treea74c3337c6ab784af77db11e11788477a2c3d5a7 /arch/powerpc/platforms
parent89491d83b27c8a713826787e40d87a4024a2cc24 (diff)
powerpc/83xx: refactor mpc8360e quirk for kmeter1
Move the code for this quirk to a dedicated function. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/83xx/km83xx.c149
1 files changed, 77 insertions, 72 deletions
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index cb6460cd96e9..88b1af04661b 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -43,6 +43,82 @@
43#include "mpc83xx.h" 43#include "mpc83xx.h"
44 44
45#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ 45#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
46
47static void quirk_mpc8360e_qe_enet10(void)
48{
49 /*
50 * handle mpc8360E Erratum QE_ENET10:
51 * RGMII AC values do not meet the specification
52 */
53 uint svid = mfspr(SPRN_SVR);
54 struct device_node *np_par;
55 struct resource res;
56 void __iomem *base;
57 int ret;
58
59 np_par = of_find_node_by_name(NULL, "par_io");
60 if (np_par == NULL) {
61 pr_warn("%s couldn;t find par_io node\n", __func__);
62 return;
63 }
64 /* Map Parallel I/O ports registers */
65 ret = of_address_to_resource(np_par, 0, &res);
66 if (ret) {
67 pr_warn("%s couldn;t map par_io registers\n", __func__);
68 return;
69 }
70
71 base = ioremap(res.start, res.end - res.start + 1);
72
73 /*
74 * set output delay adjustments to default values according
75 * table 5 in Errata Rev. 5, 9/2011:
76 *
77 * write 0b01 to UCC1 bits 18:19
78 * write 0b01 to UCC2 option 1 bits 4:5
79 * write 0b01 to UCC2 option 2 bits 16:17
80 */
81 clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
82
83 /*
84 * set output delay adjustments to default values according
85 * table 3-13 in Reference Manual Rev.3 05/2010:
86 *
87 * write 0b01 to UCC2 option 2 bits 16:17
88 * write 0b0101 to UCC1 bits 20:23
89 * write 0b0101 to UCC2 option 1 bits 24:27
90 */
91 clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
92
93 if (SVR_REV(svid) == 0x0021) {
94 /*
95 * UCC2 option 1: write 0b1010 to bits 24:27
96 * at address IMMRBAR+0x14AC
97 */
98 clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
99 } else if (SVR_REV(svid) == 0x0020) {
100 /*
101 * UCC1: write 0b11 to bits 18:19
102 * at address IMMRBAR+0x14A8
103 */
104 setbits32((base + 0xa8), 0x00003000);
105
106 /*
107 * UCC2 option 1: write 0b11 to bits 4:5
108 * at address IMMRBAR+0x14A8
109 */
110 setbits32((base + 0xa8), 0x0c000000);
111
112 /*
113 * UCC2 option 2: write 0b11 to bits 16:17
114 * at address IMMRBAR+0x14AC
115 */
116 setbits32((base + 0xac), 0x0000c000);
117 }
118 iounmap(base);
119 of_node_put(np_par);
120}
121
46/* ************************************************************************ 122/* ************************************************************************
47 * 123 *
48 * Setup the architecture 124 * Setup the architecture
@@ -73,80 +149,9 @@ static void __init mpc83xx_km_setup_arch(void)
73 for_each_node_by_name(np, "ucc") 149 for_each_node_by_name(np, "ucc")
74 par_io_of_config(np); 150 par_io_of_config(np);
75 } 151 }
76
77 np = of_find_compatible_node(NULL, "network", "ucc_geth"); 152 np = of_find_compatible_node(NULL, "network", "ucc_geth");
78 if (np != NULL) { 153 if (np != NULL) {
79 /* 154 quirk_mpc8360e_qe_enet10();
80 * handle mpc8360E Erratum QE_ENET10:
81 * RGMII AC values do not meet the specification
82 */
83 uint svid = mfspr(SPRN_SVR);
84 struct device_node *np_par;
85 struct resource res;
86 void __iomem *base;
87 int ret;
88
89 np_par = of_find_node_by_name(NULL, "par_io");
90 if (np_par == NULL) {
91 pr_warn("%s couldn;t find par_io node\n", __func__);
92 return;
93 }
94 /* Map Parallel I/O ports registers */
95 ret = of_address_to_resource(np_par, 0, &res);
96 if (ret) {
97 pr_warn("%s couldn;t map par_io registers\n", __func__);
98 return;
99 }
100
101 base = ioremap(res.start, res.end - res.start + 1);
102
103 /*
104 * set output delay adjustments to default values according
105 * table 5 in Errata Rev. 5, 9/2011:
106 *
107 * write 0b01 to UCC1 bits 18:19
108 * write 0b01 to UCC2 option 1 bits 4:5
109 * write 0b01 to UCC2 option 2 bits 16:17
110 */
111 clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
112
113 /*
114 * set output delay adjustments to default values according
115 * table 3-13 in Reference Manual Rev.3 05/2010:
116 *
117 * write 0b01 to UCC2 option 2 bits 16:17
118 * write 0b0101 to UCC1 bits 20:23
119 * write 0b0101 to UCC2 option 1 bits 24:27
120 */
121 clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
122
123 if (SVR_REV(svid) == 0x0021) {
124 /*
125 * UCC2 option 1: write 0b1010 to bits 24:27
126 * at address IMMRBAR+0x14AC
127 */
128 clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
129 } else if (SVR_REV(svid) == 0x0020) {
130 /*
131 * UCC1: write 0b11 to bits 18:19
132 * at address IMMRBAR+0x14A8
133 */
134 setbits32((base + 0xa8), 0x00003000);
135
136 /*
137 * UCC2 option 1: write 0b11 to bits 4:5
138 * at address IMMRBAR+0x14A8
139 */
140 setbits32((base + 0xa8), 0x0c000000);
141
142 /*
143 * UCC2 option 2: write 0b11 to bits 16:17
144 * at address IMMRBAR+0x14AC
145 */
146 setbits32((base + 0xac), 0x0000c000);
147 }
148 iounmap(base);
149 of_node_put(np_par);
150 of_node_put(np); 155 of_node_put(np);
151 } 156 }
152#endif /* CONFIG_QUICC_ENGINE */ 157#endif /* CONFIG_QUICC_ENGINE */
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