Merge commit 'kumar/next' into next

Conflicts:
	arch/powerpc/sysdev/fsl_msi.c

1 files changed, 99 insertions, 3 deletions

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index f0684c8ac960..8fe87fc61485 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
+ * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
  *
  * Author: Andy Fleming <afleming@freescale.com>
  *
@@ -154,6 +154,10 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
  * Setup the architecture
  *
  */
+#ifdef CONFIG_SMP
+extern void __init mpc85xx_smp_init(void);
+#endif
+
 static void __init mpc85xx_mds_setup_arch(void)
 {
         struct device_node *np;
@@ -194,6 +198,10 @@ static void __init mpc85xx_mds_setup_arch(void)
         }
 #endif
 
+#ifdef CONFIG_SMP
+        mpc85xx_smp_init();
+#endif
+
 #ifdef CONFIG_QUICC_ENGINE
         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
         if (!np) {
@@ -271,9 +279,49 @@ static void __init mpc85xx_mds_setup_arch(void)
                                                 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
                         }
 
+                } else if (machine_is(p1021_mds)) {
+#define BCSR11_ENET_MICRST     (0x1 << 5)
+                        /* Reset Micrel PHY */
+                        clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
+                        setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
                 }
+
                 iounmap(bcsr_regs);
         }
+
+        if (machine_is(p1021_mds)) {
+#define MPC85xx_PMUXCR_OFFSET           0x60
+#define MPC85xx_PMUXCR_QE0              0x00008000
+#define MPC85xx_PMUXCR_QE3              0x00001000
+#define MPC85xx_PMUXCR_QE9              0x00000040
+#define MPC85xx_PMUXCR_QE12             0x00000008
+                static __be32 __iomem *pmuxcr;
+
+                np = of_find_node_by_name(NULL, "global-utilities");
+
+                if (np) {
+                        pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
+
+                        if (!pmuxcr)
+                                printk(KERN_EMERG "Error: Alternate function"
+                                        " signal multiplex control register not"
+                                        " mapped!\n");
+                        else
+                        /* P1021 has pins muxed for QE and other functions. To
+                         * enable QE UEC mode, we need to set bit QE0 for UCC1
+                         * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+                         * and QE12 for QE MII management singals in PMUXCR
+                         * register.
+                         */
+                                setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
+                                                  MPC85xx_PMUXCR_QE3 |
+                                                  MPC85xx_PMUXCR_QE9 |
+                                                  MPC85xx_PMUXCR_QE12);
+
+                        of_node_put(np);
+                }
+
+        }
 #endif  /* CONFIG_QUICC_ENGINE */
 
 #ifdef CONFIG_SWIOTLB
@@ -330,6 +378,16 @@ static struct of_device_id mpc85xx_ids[] = {
         {},
 };
 
+static struct of_device_id p1021_ids[] = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        { .compatible = "simple-bus", },
+        { .type = "qe", },
+        { .compatible = "fsl,qe", },
+        { .compatible = "gianfar", },
+        {},
+};
+
 static int __init mpc85xx_publish_devices(void)
 {
         if (machine_is(mpc8568_mds))
@@ -342,11 +400,22 @@ static int __init mpc85xx_publish_devices(void)
 
         return 0;
 }
+
+static int __init p1021_publish_devices(void)
+{
+        /* Publish the QE devices */
+        of_platform_bus_probe(NULL, p1021_ids, NULL);
+
+        return 0;
+}
+
 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
+machine_device_initcall(p1021_mds, p1021_publish_devices);
 
 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
+machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
 
 static void __init mpc85xx_mds_pic_init(void)
 {
@@ -366,7 +435,7 @@ static void __init mpc85xx_mds_pic_init(void)
 
         mpic = mpic_alloc(np, r.start,
                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-                        MPIC_BROKEN_FRR_NIRQS,
+                        MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         of_node_put(np);
@@ -380,7 +449,11 @@ static void __init mpc85xx_mds_pic_init(void)
                 if (!np)
                         return;
         }
-        qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
+        if (machine_is(p1021_mds))
+                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+                                qe_ic_cascade_high_mpic);
+        else
+                qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
         of_node_put(np);
 #endif                          /* CONFIG_QUICC_ENGINE */
 }
@@ -426,3 +499,26 @@ define_machine(mpc8569_mds) {
         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 #endif
 };
+
+static int __init p1021_mds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
+
+}
+
+define_machine(p1021_mds) {
+        .name           = "P1021 MDS",
+        .probe          = p1021_mds_probe,
+        .setup_arch     = mpc85xx_mds_setup_arch,
+        .init_IRQ       = mpc85xx_mds_pic_init,
+        .get_irq        = mpic_get_irq,
+        .restart        = fsl_rstcr_restart,
+        .calibrate_decr = generic_calibrate_decr,
+        .progress       = udbg_progress,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+};
+