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authorLinus Torvalds <torvalds@linux-foundation.org>2008-07-22 16:16:01 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-07-22 16:16:01 -0400
commit06b8147c5dbd385b5b97ca74e19f6f3951ebc1cb (patch)
tree6ed9de7ca0ab3a65af6a189a89deb0a36ab35f6b /arch/powerpc/platforms
parent53baaaa9682c230410a057263d1ce2922f43ddc4 (diff)
parent8725f25acc656c1522d48a6746055099efdaca4c (diff)
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (49 commits) powerpc: Fix build bug with binutils < 2.18 and GCC < 4.2 powerpc/eeh: Don't panic when EEH_MAX_FAILS is exceeded fbdev: Teaches offb about palette on radeon r5xx/r6xx powerpc/cell/edac: Log a syndrome code in case of correctable error powerpc/cell: Add DMA_ATTR_WEAK_ORDERING dma attribute and use in Cell IOMMU code powerpc: Indicate which oprofile counters to use while in compat mode powerpc/boot: Change spaces to tabs powerpc: Remove duplicate 6xx option in Kconfig powerpc: Use PPC_LONG and PPC_LONG_ALIGN in lib/string.S powerpc: Use PPC_LONG_ALIGN in uaccess.h powerpc: Add a #define for aligning to a long-sized boundary powerpc: Fix OF parsing of 64 bits PCI addresses powerpc: Use WARN_ON(1) instead of __WARN() powerpc: Fix support for latencytop powerpc/ps3: Update ps3_defconfig powerpc/ps3: Add a sub-match id to ps3_system_bus powerpc: Add a 6xx defconfig powerpc/dma: Use the struct dma_attrs in iommu code powerpc/cell: Add support for power button of future IBM cell blades powerpc/cell: Cleanup sysreset_hack for IBM cell blades ...
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/52xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/82xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/82xx/ep8248e.c4
-rw-r--r--arch/powerpc/platforms/83xx/Kconfig3
-rw-r--r--arch/powerpc/platforms/83xx/Makefile2
-rw-r--r--arch/powerpc/platforms/83xx/mpc831x_rdb.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc832x_mds.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc832x_rdb.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_itx.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_mds.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc836x_mds.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc836x_rdk.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_mds.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_rdb.c1
-rw-r--r--arch/powerpc/platforms/83xx/mpc83xx.h5
-rw-r--r--arch/powerpc/platforms/83xx/pci.c91
-rw-r--r--arch/powerpc/platforms/83xx/sbc834x.c1
-rw-r--r--arch/powerpc/platforms/83xx/suspend-asm.S533
-rw-r--r--arch/powerpc/platforms/83xx/suspend.c388
-rw-r--r--arch/powerpc/platforms/83xx/usb.c24
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig3
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ds.c2
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig3
-rw-r--r--arch/powerpc/platforms/86xx/mpc8610_hpcd.c87
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c2
-rw-r--r--arch/powerpc/platforms/Kconfig6
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype5
-rw-r--r--arch/powerpc/platforms/cell/Kconfig25
-rw-r--r--arch/powerpc/platforms/cell/Makefile3
-rw-r--r--arch/powerpc/platforms/cell/cbe_powerbutton.c117
-rw-r--r--arch/powerpc/platforms/cell/cpufreq_spudemand.c184
-rw-r--r--arch/powerpc/platforms/cell/iommu.c118
-rw-r--r--arch/powerpc/platforms/cell/pervasive.c27
-rw-r--r--arch/powerpc/platforms/cell/pervasive.h9
-rw-r--r--arch/powerpc/platforms/cell/ras.c46
-rw-r--r--arch/powerpc/platforms/fsl_uli1575.c117
-rw-r--r--arch/powerpc/platforms/iseries/Kconfig1
-rw-r--r--arch/powerpc/platforms/iseries/iommu.c3
-rw-r--r--arch/powerpc/platforms/pasemi/iommu.c3
-rw-r--r--arch/powerpc/platforms/ps3/Kconfig1
-rw-r--r--arch/powerpc/platforms/ps3/device-init.c1
-rw-r--r--arch/powerpc/platforms/ps3/system-bus.c21
-rw-r--r--arch/powerpc/platforms/pseries/Kconfig1
-rw-r--r--arch/powerpc/platforms/pseries/eeh.c26
-rw-r--r--arch/powerpc/platforms/pseries/iommu.c14
45 files changed, 1609 insertions, 278 deletions
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index acd2fc8cf492..d664b1bce381 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -3,6 +3,7 @@ config PPC_MPC52xx
3 depends on PPC_MULTIPLATFORM && PPC32 3 depends on PPC_MULTIPLATFORM && PPC32
4 select FSL_SOC 4 select FSL_SOC
5 select PPC_CLOCK 5 select PPC_CLOCK
6 select PPC_PCI_CHOICE
6 7
7config PPC_MPC5200_SIMPLE 8config PPC_MPC5200_SIMPLE
8 bool "Generic support for simple MPC5200 based boards" 9 bool "Generic support for simple MPC5200 based boards"
diff --git a/arch/powerpc/platforms/82xx/Kconfig b/arch/powerpc/platforms/82xx/Kconfig
index 1c8034bfa796..75eb1ede5497 100644
--- a/arch/powerpc/platforms/82xx/Kconfig
+++ b/arch/powerpc/platforms/82xx/Kconfig
@@ -30,6 +30,7 @@ config EP8248E
30 select 8272 30 select 8272
31 select 8260 31 select 8260
32 select FSL_SOC 32 select FSL_SOC
33 select PHYLIB
33 select MDIO_BITBANG 34 select MDIO_BITBANG
34 help 35 help
35 This enables support for the Embedded Planet EP8248E board. 36 This enables support for the Embedded Planet EP8248E board.
diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
index 373e993a5ed5..d5770fdf7f09 100644
--- a/arch/powerpc/platforms/82xx/ep8248e.c
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -59,7 +59,6 @@ static void __init ep8248e_pic_init(void)
59 of_node_put(np); 59 of_node_put(np);
60} 60}
61 61
62#ifdef CONFIG_FS_ENET_MDIO_FCC
63static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level) 62static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level)
64{ 63{
65 if (level) 64 if (level)
@@ -165,7 +164,6 @@ static struct of_platform_driver ep8248e_mdio_driver = {
165 .probe = ep8248e_mdio_probe, 164 .probe = ep8248e_mdio_probe,
166 .remove = ep8248e_mdio_remove, 165 .remove = ep8248e_mdio_remove,
167}; 166};
168#endif
169 167
170struct cpm_pin { 168struct cpm_pin {
171 int port, pin, flags; 169 int port, pin, flags;
@@ -298,9 +296,7 @@ static __initdata struct of_device_id of_bus_ids[] = {
298static int __init declare_of_platform_devices(void) 296static int __init declare_of_platform_devices(void)
299{ 297{
300 of_platform_bus_probe(NULL, of_bus_ids, NULL); 298 of_platform_bus_probe(NULL, of_bus_ids, NULL);
301#ifdef CONFIG_FS_ENET_MDIO_FCC
302 of_register_platform_driver(&ep8248e_mdio_driver); 299 of_register_platform_driver(&ep8248e_mdio_driver);
303#endif
304 300
305 return 0; 301 return 0;
306} 302}
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 27d9bf86de01..6159c5d4e5f1 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -2,7 +2,8 @@ menuconfig PPC_83xx
2 bool "83xx-based boards" 2 bool "83xx-based boards"
3 depends on 6xx && PPC_MULTIPLATFORM 3 depends on 6xx && PPC_MULTIPLATFORM
4 select PPC_UDBG_16550 4 select PPC_UDBG_16550
5 select PPC_INDIRECT_PCI 5 select PPC_PCI_CHOICE
6 select FSL_PCI if PCI
6 select FSL_SOC 7 select FSL_SOC
7 select IPIC 8 select IPIC
8 9
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index f331fd7dd836..ba5028e29890 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the PowerPC 83xx linux kernel. 2# Makefile for the PowerPC 83xx linux kernel.
3# 3#
4obj-y := misc.o usb.o 4obj-y := misc.o usb.o
5obj-$(CONFIG_PCI) += pci.o 5obj-$(CONFIG_SUSPEND) += suspend.o suspend-asm.o
6obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o 6obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
7obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o 7obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
8obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o 8obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
index c4db5172b27a..a428f8d1ac80 100644
--- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
@@ -19,6 +19,7 @@
19#include <asm/time.h> 19#include <asm/time.h>
20#include <asm/ipic.h> 20#include <asm/ipic.h>
21#include <asm/udbg.h> 21#include <asm/udbg.h>
22#include <sysdev/fsl_pci.h>
22 23
23#include "mpc83xx.h" 24#include "mpc83xx.h"
24 25
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index 6dbc6eabcb02..dd4be4aee314 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -36,6 +36,7 @@
36#include <asm/prom.h> 36#include <asm/prom.h>
37#include <asm/udbg.h> 37#include <asm/udbg.h>
38#include <sysdev/fsl_soc.h> 38#include <sysdev/fsl_soc.h>
39#include <sysdev/fsl_pci.h>
39#include <asm/qe.h> 40#include <asm/qe.h>
40#include <asm/qe_ic.h> 41#include <asm/qe_ic.h>
41 42
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index e7f706b624fe..f049d692d4c8 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -27,6 +27,7 @@
27#include <asm/qe.h> 27#include <asm/qe.h>
28#include <asm/qe_ic.h> 28#include <asm/qe_ic.h>
29#include <sysdev/fsl_soc.h> 29#include <sysdev/fsl_soc.h>
30#include <sysdev/fsl_pci.h>
30 31
31#include "mpc83xx.h" 32#include "mpc83xx.h"
32 33
diff --git a/arch/powerpc/platforms/83xx/mpc834x_itx.c b/arch/powerpc/platforms/83xx/mpc834x_itx.c
index 50e8f632061c..7301d77a08ee 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_itx.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_itx.c
@@ -35,6 +35,7 @@
35#include <asm/prom.h> 35#include <asm/prom.h>
36#include <asm/udbg.h> 36#include <asm/udbg.h>
37#include <sysdev/fsl_soc.h> 37#include <sysdev/fsl_soc.h>
38#include <sysdev/fsl_pci.h>
38 39
39#include "mpc83xx.h" 40#include "mpc83xx.h"
40 41
diff --git a/arch/powerpc/platforms/83xx/mpc834x_mds.c b/arch/powerpc/platforms/83xx/mpc834x_mds.c
index 2b8a0a3f8557..30d509aa9f08 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_mds.c
@@ -35,6 +35,7 @@
35#include <asm/prom.h> 35#include <asm/prom.h>
36#include <asm/udbg.h> 36#include <asm/udbg.h>
37#include <sysdev/fsl_soc.h> 37#include <sysdev/fsl_soc.h>
38#include <sysdev/fsl_pci.h>
38 39
39#include "mpc83xx.h" 40#include "mpc83xx.h"
40 41
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index c2e5de60c055..75b80e836576 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -42,6 +42,7 @@
42#include <asm/prom.h> 42#include <asm/prom.h>
43#include <asm/udbg.h> 43#include <asm/udbg.h>
44#include <sysdev/fsl_soc.h> 44#include <sysdev/fsl_soc.h>
45#include <sysdev/fsl_pci.h>
45#include <asm/qe.h> 46#include <asm/qe.h>
46#include <asm/qe_ic.h> 47#include <asm/qe_ic.h>
47 48
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index c10dec4bf178..a5273bb28e1b 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -23,6 +23,7 @@
23#include <asm/qe.h> 23#include <asm/qe.h>
24#include <asm/qe_ic.h> 24#include <asm/qe_ic.h>
25#include <sysdev/fsl_soc.h> 25#include <sysdev/fsl_soc.h>
26#include <sysdev/fsl_pci.h>
26 27
27#include "mpc83xx.h" 28#include "mpc83xx.h"
28 29
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index 64d17b0d6455..be62de23bead 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -19,6 +19,7 @@
19#include <asm/ipic.h> 19#include <asm/ipic.h>
20#include <asm/udbg.h> 20#include <asm/udbg.h>
21#include <asm/prom.h> 21#include <asm/prom.h>
22#include <sysdev/fsl_pci.h>
22 23
23#include "mpc83xx.h" 24#include "mpc83xx.h"
24 25
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index c00356bdb1dd..da030afa2e2c 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -17,6 +17,7 @@
17#include <asm/time.h> 17#include <asm/time.h>
18#include <asm/ipic.h> 18#include <asm/ipic.h>
19#include <asm/udbg.h> 19#include <asm/udbg.h>
20#include <sysdev/fsl_pci.h>
20 21
21#include "mpc83xx.h" 22#include "mpc83xx.h"
22 23
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 88a3b5cabb18..2a7cbabb410a 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -26,6 +26,8 @@
26#define MPC834X_SICRL_USB1 0x20000000 26#define MPC834X_SICRL_USB1 0x20000000
27#define MPC831X_SICRL_USB_MASK 0x00000c00 27#define MPC831X_SICRL_USB_MASK 0x00000c00
28#define MPC831X_SICRL_USB_ULPI 0x00000800 28#define MPC831X_SICRL_USB_ULPI 0x00000800
29#define MPC8315_SICRL_USB_MASK 0x000000fc
30#define MPC8315_SICRL_USB_ULPI 0x00000054
29#define MPC837X_SICRL_USB_MASK 0xf0000000 31#define MPC837X_SICRL_USB_MASK 0xf0000000
30#define MPC837X_SICRL_USB_ULPI 0x50000000 32#define MPC837X_SICRL_USB_ULPI 0x50000000
31 33
@@ -34,6 +36,8 @@
34#define MPC834X_SICRH_USB_UTMI 0x00020000 36#define MPC834X_SICRH_USB_UTMI 0x00020000
35#define MPC831X_SICRH_USB_MASK 0x000000e0 37#define MPC831X_SICRH_USB_MASK 0x000000e0
36#define MPC831X_SICRH_USB_ULPI 0x000000a0 38#define MPC831X_SICRH_USB_ULPI 0x000000a0
39#define MPC8315_SICRH_USB_MASK 0x0000ff00
40#define MPC8315_SICRH_USB_ULPI 0x00000000
37 41
38/* USB Control Register */ 42/* USB Control Register */
39#define FSL_USB2_CONTROL_OFFS 0x500 43#define FSL_USB2_CONTROL_OFFS 0x500
@@ -55,7 +59,6 @@
55 * mpc83xx_* files. Mostly for use by mpc83xx_setup 59 * mpc83xx_* files. Mostly for use by mpc83xx_setup
56 */ 60 */
57 61
58extern int mpc83xx_add_bridge(struct device_node *dev);
59extern void mpc83xx_restart(char *cmd); 62extern void mpc83xx_restart(char *cmd);
60extern long mpc83xx_time_init(void); 63extern long mpc83xx_time_init(void);
61extern int mpc834x_usb_cfg(void); 64extern int mpc834x_usb_cfg(void);
diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c
deleted file mode 100644
index 14f1080c6c9d..000000000000
--- a/arch/powerpc/platforms/83xx/pci.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * FSL SoC setup code
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/stddef.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/irq.h>
19#include <linux/module.h>
20
21#include <asm/system.h>
22#include <asm/atomic.h>
23#include <asm/io.h>
24#include <asm/pci-bridge.h>
25#include <asm/prom.h>
26#include <sysdev/fsl_soc.h>
27
28#undef DEBUG
29
30#ifdef DEBUG
31#define DBG(x...) printk(x)
32#else
33#define DBG(x...)
34#endif
35
36int __init mpc83xx_add_bridge(struct device_node *dev)
37{
38 int len;
39 struct pci_controller *hose;
40 struct resource rsrc;
41 const int *bus_range;
42 int primary = 1, has_address = 0;
43 phys_addr_t immr = get_immrbase();
44
45 DBG("Adding PCI host bridge %s\n", dev->full_name);
46
47 /* Fetch host bridge registers address */
48 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
49
50 /* Get bus range if any */
51 bus_range = of_get_property(dev, "bus-range", &len);
52 if (bus_range == NULL || len < 2 * sizeof(int)) {
53 printk(KERN_WARNING "Can't get bus-range for %s, assume"
54 " bus 0\n", dev->full_name);
55 }
56
57 ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
58 hose = pcibios_alloc_controller(dev);
59 if (!hose)
60 return -ENOMEM;
61
62 hose->first_busno = bus_range ? bus_range[0] : 0;
63 hose->last_busno = bus_range ? bus_range[1] : 0xff;
64
65 /* MPC83xx supports up to two host controllers one at 0x8500 from immrbar
66 * the other at 0x8600, we consider the 0x8500 the primary controller
67 */
68 /* PCI 1 */
69 if ((rsrc.start & 0xfffff) == 0x8500) {
70 setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
71 }
72 /* PCI 2 */
73 if ((rsrc.start & 0xfffff) == 0x8600) {
74 setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0);
75 primary = 0;
76 }
77
78 printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
79 "Firmware bus number: %d->%d\n",
80 (unsigned long long)rsrc.start, hose->first_busno,
81 hose->last_busno);
82
83 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
84 hose, hose->cfg_addr, hose->cfg_data);
85
86 /* Interpret the "ranges" property */
87 /* This also maps the I/O region and sets isa_io/mem_base */
88 pci_process_bridge_OF_ranges(hose, dev, primary);
89
90 return 0;
91}
diff --git a/arch/powerpc/platforms/83xx/sbc834x.c b/arch/powerpc/platforms/83xx/sbc834x.c
index cf382474a83d..fc21f5c15bab 100644
--- a/arch/powerpc/platforms/83xx/sbc834x.c
+++ b/arch/powerpc/platforms/83xx/sbc834x.c
@@ -37,6 +37,7 @@
37#include <asm/prom.h> 37#include <asm/prom.h>
38#include <asm/udbg.h> 38#include <asm/udbg.h>
39#include <sysdev/fsl_soc.h> 39#include <sysdev/fsl_soc.h>
40#include <sysdev/fsl_pci.h>
40 41
41#include "mpc83xx.h" 42#include "mpc83xx.h"
42 43
diff --git a/arch/powerpc/platforms/83xx/suspend-asm.S b/arch/powerpc/platforms/83xx/suspend-asm.S
new file mode 100644
index 000000000000..1930543c98d3
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/suspend-asm.S
@@ -0,0 +1,533 @@
1/*
2 * Enter and leave deep sleep state on MPC83xx
3 *
4 * Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
5 * Author: Scott Wood <scottwood@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <asm/page.h>
13#include <asm/ppc_asm.h>
14#include <asm/reg.h>
15#include <asm/asm-offsets.h>
16
17#define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
18#define SS_HID 0x08 /* 3 HIDs */
19#define SS_IABR 0x14 /* 2 IABRs */
20#define SS_IBCR 0x1c
21#define SS_DABR 0x20 /* 2 DABRs */
22#define SS_DBCR 0x28
23#define SS_SP 0x2c
24#define SS_SR 0x30 /* 16 segment registers */
25#define SS_R2 0x70
26#define SS_MSR 0x74
27#define SS_SDR1 0x78
28#define SS_LR 0x7c
29#define SS_SPRG 0x80 /* 4 SPRGs */
30#define SS_DBAT 0x90 /* 8 DBATs */
31#define SS_IBAT 0xd0 /* 8 IBATs */
32#define SS_TB 0x110
33#define SS_CR 0x118
34#define SS_GPREG 0x11c /* r12-r31 */
35#define STATE_SAVE_SIZE 0x16c
36
37 .section .data
38 .align 5
39
40mpc83xx_sleep_save_area:
41 .space STATE_SAVE_SIZE
42immrbase:
43 .long 0
44
45 .section .text
46 .align 5
47
48 /* r3 = physical address of IMMR */
49_GLOBAL(mpc83xx_enter_deep_sleep)
50 lis r4, immrbase@ha
51 stw r3, immrbase@l(r4)
52
53 /* The first 2 words of memory are used to communicate with the
54 * bootloader, to tell it how to resume.
55 *
56 * The first word is the magic number 0xf5153ae5, and the second
57 * is the pointer to mpc83xx_deep_resume.
58 *
59 * The original content of these two words is saved in SS_MEMSAVE.
60 */
61
62 lis r3, mpc83xx_sleep_save_area@h
63 ori r3, r3, mpc83xx_sleep_save_area@l
64
65 lis r4, KERNELBASE@h
66 lwz r5, 0(r4)
67 lwz r6, 4(r4)
68
69 stw r5, SS_MEMSAVE+0(r3)
70 stw r6, SS_MEMSAVE+4(r3)
71
72 mfspr r5, SPRN_HID0
73 mfspr r6, SPRN_HID1
74 mfspr r7, SPRN_HID2
75
76 stw r5, SS_HID+0(r3)
77 stw r6, SS_HID+4(r3)
78 stw r7, SS_HID+8(r3)
79
80 mfspr r4, SPRN_IABR
81 mfspr r5, SPRN_IABR2
82 mfspr r6, SPRN_IBCR
83 mfspr r7, SPRN_DABR
84 mfspr r8, SPRN_DABR2
85 mfspr r9, SPRN_DBCR
86
87 stw r4, SS_IABR+0(r3)
88 stw r5, SS_IABR+4(r3)
89 stw r6, SS_IBCR(r3)
90 stw r7, SS_DABR+0(r3)
91 stw r8, SS_DABR+4(r3)
92 stw r9, SS_DBCR(r3)
93
94 mfspr r4, SPRN_SPRG0
95 mfspr r5, SPRN_SPRG1
96 mfspr r6, SPRN_SPRG2
97 mfspr r7, SPRN_SPRG3
98 mfsdr1 r8
99
100 stw r4, SS_SPRG+0(r3)
101 stw r5, SS_SPRG+4(r3)
102 stw r6, SS_SPRG+8(r3)
103 stw r7, SS_SPRG+12(r3)
104 stw r8, SS_SDR1(r3)
105
106 mfspr r4, SPRN_DBAT0U
107 mfspr r5, SPRN_DBAT0L
108 mfspr r6, SPRN_DBAT1U
109 mfspr r7, SPRN_DBAT1L
110
111 stw r4, SS_DBAT+0x00(r3)
112 stw r5, SS_DBAT+0x04(r3)
113 stw r6, SS_DBAT+0x08(r3)
114 stw r7, SS_DBAT+0x0c(r3)
115
116 mfspr r4, SPRN_DBAT2U
117 mfspr r5, SPRN_DBAT2L
118 mfspr r6, SPRN_DBAT3U
119 mfspr r7, SPRN_DBAT3L
120
121 stw r4, SS_DBAT+0x10(r3)
122 stw r5, SS_DBAT+0x14(r3)
123 stw r6, SS_DBAT+0x18(r3)
124 stw r7, SS_DBAT+0x1c(r3)
125
126 mfspr r4, SPRN_DBAT4U
127 mfspr r5, SPRN_DBAT4L
128 mfspr r6, SPRN_DBAT5U
129 mfspr r7, SPRN_DBAT5L
130
131 stw r4, SS_DBAT+0x20(r3)
132 stw r5, SS_DBAT+0x24(r3)
133 stw r6, SS_DBAT+0x28(r3)
134 stw r7, SS_DBAT+0x2c(r3)
135
136 mfspr r4, SPRN_DBAT6U
137 mfspr r5, SPRN_DBAT6L
138 mfspr r6, SPRN_DBAT7U
139 mfspr r7, SPRN_DBAT7L
140
141 stw r4, SS_DBAT+0x30(r3)
142 stw r5, SS_DBAT+0x34(r3)
143 stw r6, SS_DBAT+0x38(r3)
144 stw r7, SS_DBAT+0x3c(r3)
145
146 mfspr r4, SPRN_IBAT0U
147 mfspr r5, SPRN_IBAT0L
148 mfspr r6, SPRN_IBAT1U
149 mfspr r7, SPRN_IBAT1L
150
151 stw r4, SS_IBAT+0x00(r3)
152 stw r5, SS_IBAT+0x04(r3)
153 stw r6, SS_IBAT+0x08(r3)
154 stw r7, SS_IBAT+0x0c(r3)
155
156 mfspr r4, SPRN_IBAT2U
157 mfspr r5, SPRN_IBAT2L
158 mfspr r6, SPRN_IBAT3U
159 mfspr r7, SPRN_IBAT3L
160
161 stw r4, SS_IBAT+0x10(r3)
162 stw r5, SS_IBAT+0x14(r3)
163 stw r6, SS_IBAT+0x18(r3)
164 stw r7, SS_IBAT+0x1c(r3)
165
166 mfspr r4, SPRN_IBAT4U
167 mfspr r5, SPRN_IBAT4L
168 mfspr r6, SPRN_IBAT5U
169 mfspr r7, SPRN_IBAT5L
170
171 stw r4, SS_IBAT+0x20(r3)
172 stw r5, SS_IBAT+0x24(r3)
173 stw r6, SS_IBAT+0x28(r3)
174 stw r7, SS_IBAT+0x2c(r3)
175
176 mfspr r4, SPRN_IBAT6U
177 mfspr r5, SPRN_IBAT6L
178 mfspr r6, SPRN_IBAT7U
179 mfspr r7, SPRN_IBAT7L
180
181 stw r4, SS_IBAT+0x30(r3)
182 stw r5, SS_IBAT+0x34(r3)
183 stw r6, SS_IBAT+0x38(r3)
184 stw r7, SS_IBAT+0x3c(r3)
185
186 mfmsr r4
187 mflr r5
188 mfcr r6
189
190 stw r4, SS_MSR(r3)
191 stw r5, SS_LR(r3)
192 stw r6, SS_CR(r3)
193 stw r1, SS_SP(r3)
194 stw r2, SS_R2(r3)
195
1961: mftbu r4
197 mftb r5
198 mftbu r6
199 cmpw r4, r6
200 bne 1b
201
202 stw r4, SS_TB+0(r3)
203 stw r5, SS_TB+4(r3)
204
205 stmw r12, SS_GPREG(r3)
206
207 li r4, 0
208 addi r6, r3, SS_SR-4
2091: mfsrin r5, r4
210 stwu r5, 4(r6)
211 addis r4, r4, 0x1000
212 cmpwi r4, 0
213 bne 1b
214
215 /* Disable machine checks and critical exceptions */
216 mfmsr r4
217 rlwinm r4, r4, 0, ~MSR_CE
218 rlwinm r4, r4, 0, ~MSR_ME
219 mtmsr r4
220 isync
221
222#define TMP_VIRT_IMMR 0xf0000000
223#define DEFAULT_IMMR_VALUE 0xff400000
224#define IMMRBAR_BASE 0x0000
225
226 lis r4, immrbase@ha
227 lwz r4, immrbase@l(r4)
228
229 /* Use DBAT0 to address the current IMMR space */
230
231 ori r4, r4, 0x002a
232 mtspr SPRN_DBAT0L, r4
233 lis r8, TMP_VIRT_IMMR@h
234 ori r4, r8, 0x001e /* 1 MByte accessable from Kernel Space only */
235 mtspr SPRN_DBAT0U, r4
236 isync
237
238 /* Use DBAT1 to address the original IMMR space */
239
240 lis r4, DEFAULT_IMMR_VALUE@h
241 ori r4, r4, 0x002a
242 mtspr SPRN_DBAT1L, r4
243 lis r9, (TMP_VIRT_IMMR + 0x01000000)@h
244 ori r4, r9, 0x001e /* 1 MByte accessable from Kernel Space only */
245 mtspr SPRN_DBAT1U, r4
246 isync
247
248 /* Use DBAT2 to address the beginning of RAM. This isn't done
249 * using the normal virtual mapping, because with page debugging
250 * enabled it will be read-only.
251 */
252
253 li r4, 0x0002
254 mtspr SPRN_DBAT2L, r4
255 lis r4, KERNELBASE@h
256 ori r4, r4, 0x001e /* 1 MByte accessable from Kernel Space only */
257 mtspr SPRN_DBAT2U, r4
258 isync
259
260 /* Flush the cache with our BAT, as there will be TLB misses
261 * otherwise if page debugging is enabled, and these misses
262 * will disturb the PLRU algorithm.
263 */
264
265 bl __flush_disable_L1
266
267 /* Keep the i-cache enabled, so the hack below for low-boot
268 * flash will work.
269 */
270 mfspr r3, SPRN_HID0
271 ori r3, r3, HID0_ICE
272 mtspr SPRN_HID0, r3
273 isync
274
275 lis r6, 0xf515
276 ori r6, r6, 0x3ae5
277
278 lis r7, mpc83xx_deep_resume@h
279 ori r7, r7, mpc83xx_deep_resume@l
280 tophys(r7, r7)
281
282 lis r5, KERNELBASE@h
283 stw r6, 0(r5)
284 stw r7, 4(r5)
285
286 /* Reset BARs */
287
288 li r4, 0
289 stw r4, 0x0024(r8)
290 stw r4, 0x002c(r8)
291 stw r4, 0x0034(r8)
292 stw r4, 0x003c(r8)
293 stw r4, 0x0064(r8)
294 stw r4, 0x006c(r8)
295
296 /* Rev 1 of the 8313 has problems with wakeup events that are
297 * pending during the transition to deep sleep state (such as if
298 * the PCI host sets the state to D3 and then D0 in rapid
299 * succession). This check shrinks the race window somewhat.
300 *
301 * See erratum PCI23, though the problem is not limited
302 * to PCI.
303 */
304
305 lwz r3, 0x0b04(r8)
306 andi. r3, r3, 1
307 bne- mpc83xx_deep_resume
308
309 /* Move IMMR back to the default location, following the
310 * procedure specified in the MPC8313 manual.
311 */
312 lwz r4, IMMRBAR_BASE(r8)
313 isync
314 lis r4, DEFAULT_IMMR_VALUE@h
315 stw r4, IMMRBAR_BASE(r8)
316 lis r4, KERNELBASE@h
317 lwz r4, 0(r4)
318 isync
319 lwz r4, IMMRBAR_BASE(r9)
320 mr r8, r9
321 isync
322
323 /* Check the Reset Configuration Word to see whether flash needs
324 * to be mapped at a low address or a high address.
325 */
326
327 lwz r4, 0x0904(r8)
328 andis. r4, r4, 0x0400
329 li r4, 0
330 beq boot_low
331 lis r4, 0xff80
332boot_low:
333 stw r4, 0x0020(r8)
334 lis r7, 0x8000
335 ori r7, r7, 0x0016
336
337 mfspr r5, SPRN_HID0
338 rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
339 oris r5, r5, HID0_SLEEP@h
340 mtspr SPRN_HID0, r5
341 isync
342
343 mfmsr r5
344 oris r5, r5, MSR_POW@h
345
346 /* Enable the flash mapping at the appropriate address. This
347 * mapping will override the RAM mapping if booting low, so there's
348 * no need to disable the latter. This must be done inside the same
349 * cache line as setting MSR_POW, so that no instruction fetches
350 * from RAM happen after the flash mapping is turned on.
351 */
352
353 .align 5
354 stw r7, 0x0024(r8)
355 sync
356 isync
357 mtmsr r5
358 isync
3591: b 1b
360
361mpc83xx_deep_resume:
362 lis r4, 1f@h
363 ori r4, r4, 1f@l
364 tophys(r4, r4)
365 mtsrr0 r4
366
367 mfmsr r4
368 rlwinm r4, r4, 0, ~(MSR_IR | MSR_DR)
369 mtsrr1 r4
370
371 rfi
372
3731: tlbia
374 bl __inval_enable_L1
375
376 lis r3, mpc83xx_sleep_save_area@h
377 ori r3, r3, mpc83xx_sleep_save_area@l
378 tophys(r3, r3)
379
380 lwz r5, SS_MEMSAVE+0(r3)
381 lwz r6, SS_MEMSAVE+4(r3)
382
383 stw r5, 0(0)
384 stw r6, 4(0)
385
386 lwz r5, SS_HID+0(r3)
387 lwz r6, SS_HID+4(r3)
388 lwz r7, SS_HID+8(r3)
389
390 mtspr SPRN_HID0, r5
391 mtspr SPRN_HID1, r6
392 mtspr SPRN_HID2, r7
393
394 lwz r4, SS_IABR+0(r3)
395 lwz r5, SS_IABR+4(r3)
396 lwz r6, SS_IBCR(r3)
397 lwz r7, SS_DABR+0(r3)
398 lwz r8, SS_DABR+4(r3)
399 lwz r9, SS_DBCR(r3)
400
401 mtspr SPRN_IABR, r4
402 mtspr SPRN_IABR2, r5
403 mtspr SPRN_IBCR, r6
404 mtspr SPRN_DABR, r7
405 mtspr SPRN_DABR2, r8
406 mtspr SPRN_DBCR, r9
407
408 li r4, 0
409 addi r6, r3, SS_SR-4
4101: lwzu r5, 4(r6)
411 mtsrin r5, r4
412 addis r4, r4, 0x1000
413 cmpwi r4, 0
414 bne 1b
415
416 lwz r4, SS_DBAT+0x00(r3)
417 lwz r5, SS_DBAT+0x04(r3)
418 lwz r6, SS_DBAT+0x08(r3)
419 lwz r7, SS_DBAT+0x0c(r3)
420
421 mtspr SPRN_DBAT0U, r4
422 mtspr SPRN_DBAT0L, r5
423 mtspr SPRN_DBAT1U, r6
424 mtspr SPRN_DBAT1L, r7
425
426 lwz r4, SS_DBAT+0x10(r3)
427 lwz r5, SS_DBAT+0x14(r3)
428 lwz r6, SS_DBAT+0x18(r3)
429 lwz r7, SS_DBAT+0x1c(r3)
430
431 mtspr SPRN_DBAT2U, r4
432 mtspr SPRN_DBAT2L, r5
433 mtspr SPRN_DBAT3U, r6
434 mtspr SPRN_DBAT3L, r7
435
436 lwz r4, SS_DBAT+0x20(r3)
437 lwz r5, SS_DBAT+0x24(r3)
438 lwz r6, SS_DBAT+0x28(r3)
439 lwz r7, SS_DBAT+0x2c(r3)
440
441 mtspr SPRN_DBAT4U, r4
442 mtspr SPRN_DBAT4L, r5
443 mtspr SPRN_DBAT5U, r6
444 mtspr SPRN_DBAT5L, r7
445
446 lwz r4, SS_DBAT+0x30(r3)
447 lwz r5, SS_DBAT+0x34(r3)
448 lwz r6, SS_DBAT+0x38(r3)
449 lwz r7, SS_DBAT+0x3c(r3)
450
451 mtspr SPRN_DBAT6U, r4
452 mtspr SPRN_DBAT6L, r5
453 mtspr SPRN_DBAT7U, r6
454 mtspr SPRN_DBAT7L, r7
455
456 lwz r4, SS_IBAT+0x00(r3)
457 lwz r5, SS_IBAT+0x04(r3)
458 lwz r6, SS_IBAT+0x08(r3)
459 lwz r7, SS_IBAT+0x0c(r3)
460
461 mtspr SPRN_IBAT0U, r4
462 mtspr SPRN_IBAT0L, r5
463 mtspr SPRN_IBAT1U, r6
464 mtspr SPRN_IBAT1L, r7
465
466 lwz r4, SS_IBAT+0x10(r3)
467 lwz r5, SS_IBAT+0x14(r3)
468 lwz r6, SS_IBAT+0x18(r3)
469 lwz r7, SS_IBAT+0x1c(r3)
470
471 mtspr SPRN_IBAT2U, r4
472 mtspr SPRN_IBAT2L, r5
473 mtspr SPRN_IBAT3U, r6
474 mtspr SPRN_IBAT3L, r7
475
476 lwz r4, SS_IBAT+0x20(r3)
477 lwz r5, SS_IBAT+0x24(r3)
478 lwz r6, SS_IBAT+0x28(r3)
479 lwz r7, SS_IBAT+0x2c(r3)
480
481 mtspr SPRN_IBAT4U, r4
482 mtspr SPRN_IBAT4L, r5
483 mtspr SPRN_IBAT5U, r6
484 mtspr SPRN_IBAT5L, r7
485
486 lwz r4, SS_IBAT+0x30(r3)
487 lwz r5, SS_IBAT+0x34(r3)
488 lwz r6, SS_IBAT+0x38(r3)
489 lwz r7, SS_IBAT+0x3c(r3)
490
491 mtspr SPRN_IBAT6U, r4
492 mtspr SPRN_IBAT6L, r5
493 mtspr SPRN_IBAT7U, r6
494 mtspr SPRN_IBAT7L, r7
495
496 lwz r4, SS_SPRG+0(r3)
497 lwz r5, SS_SPRG+4(r3)
498 lwz r6, SS_SPRG+8(r3)
499 lwz r7, SS_SPRG+12(r3)
500 lwz r8, SS_SDR1(r3)
501
502 mtspr SPRN_SPRG0, r4
503 mtspr SPRN_SPRG1, r5
504 mtspr SPRN_SPRG2, r6
505 mtspr SPRN_SPRG3, r7
506 mtsdr1 r8
507
508 lwz r4, SS_MSR(r3)
509 lwz r5, SS_LR(r3)
510 lwz r6, SS_CR(r3)
511 lwz r1, SS_SP(r3)
512 lwz r2, SS_R2(r3)
513
514 mtsrr1 r4
515 mtsrr0 r5
516 mtcr r6
517
518 li r4, 0
519 mtspr SPRN_TBWL, r4
520
521 lwz r4, SS_TB+0(r3)
522 lwz r5, SS_TB+4(r3)
523
524 mtspr SPRN_TBWU, r4
525 mtspr SPRN_TBWL, r5
526
527 lmw r12, SS_GPREG(r3)
528
529 /* Kick decrementer */
530 li r0, 1
531 mtdec r0
532
533 rfi
diff --git a/arch/powerpc/platforms/83xx/suspend.c b/arch/powerpc/platforms/83xx/suspend.c
new file mode 100644
index 000000000000..08e65fc8b98c
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/suspend.c
@@ -0,0 +1,388 @@
1/*
2 * MPC83xx suspend support
3 *
4 * Author: Scott Wood <scottwood@freescale.com>
5 *
6 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/pm.h>
15#include <linux/types.h>
16#include <linux/ioport.h>
17#include <linux/interrupt.h>
18#include <linux/wait.h>
19#include <linux/kthread.h>
20#include <linux/freezer.h>
21#include <linux/suspend.h>
22#include <linux/fsl_devices.h>
23#include <linux/of_platform.h>
24
25#include <asm/reg.h>
26#include <asm/io.h>
27#include <asm/time.h>
28#include <asm/mpc6xx.h>
29
30#include <sysdev/fsl_soc.h>
31
32#define PMCCR1_NEXT_STATE 0x0C /* Next state for power management */
33#define PMCCR1_NEXT_STATE_SHIFT 2
34#define PMCCR1_CURR_STATE 0x03 /* Current state for power management*/
35#define IMMR_RCW_OFFSET 0x900
36#define RCW_PCI_HOST 0x80000000
37
38void mpc83xx_enter_deep_sleep(phys_addr_t immrbase);
39
40struct mpc83xx_pmc {
41 u32 config;
42#define PMCCR_DLPEN 2 /* DDR SDRAM low power enable */
43#define PMCCR_SLPEN 1 /* System low power enable */
44
45 u32 event;
46 u32 mask;
47/* All but PMCI are deep-sleep only */
48#define PMCER_GPIO 0x100
49#define PMCER_PCI 0x080
50#define PMCER_USB 0x040
51#define PMCER_ETSEC1 0x020
52#define PMCER_ETSEC2 0x010
53#define PMCER_TIMER 0x008
54#define PMCER_INT1 0x004
55#define PMCER_INT2 0x002
56#define PMCER_PMCI 0x001
57#define PMCER_ALL 0x1FF
58
59 /* deep-sleep only */
60 u32 config1;
61#define PMCCR1_USE_STATE 0x80000000
62#define PMCCR1_PME_EN 0x00000080
63#define PMCCR1_ASSERT_PME 0x00000040
64#define PMCCR1_POWER_OFF 0x00000020
65
66 /* deep-sleep only */
67 u32 config2;
68};
69
70struct mpc83xx_rcw {
71 u32 rcwlr;
72 u32 rcwhr;
73};
74
75struct mpc83xx_clock {
76 u32 spmr;
77 u32 occr;
78 u32 sccr;
79};
80
81struct pmc_type {
82 int has_deep_sleep;
83};
84
85static struct of_device *pmc_dev;
86static int has_deep_sleep, deep_sleeping;
87static int pmc_irq;
88static struct mpc83xx_pmc __iomem *pmc_regs;
89static struct mpc83xx_clock __iomem *clock_regs;
90static int is_pci_agent, wake_from_pci;
91static phys_addr_t immrbase;
92static int pci_pm_state;
93static DECLARE_WAIT_QUEUE_HEAD(agent_wq);
94
95int fsl_deep_sleep(void)
96{
97 return deep_sleeping;
98}
99
100static int mpc83xx_change_state(void)
101{
102 u32 curr_state;
103 u32 reg_cfg1 = in_be32(&pmc_regs->config1);
104
105 if (is_pci_agent) {
106 pci_pm_state = (reg_cfg1 & PMCCR1_NEXT_STATE) >>
107 PMCCR1_NEXT_STATE_SHIFT;
108 curr_state = reg_cfg1 & PMCCR1_CURR_STATE;
109
110 if (curr_state != pci_pm_state) {
111 reg_cfg1 &= ~PMCCR1_CURR_STATE;
112 reg_cfg1 |= pci_pm_state;
113 out_be32(&pmc_regs->config1, reg_cfg1);
114
115 wake_up(&agent_wq);
116 return 1;
117 }
118 }
119
120 return 0;
121}
122
123static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
124{
125 u32 event = in_be32(&pmc_regs->event);
126 int ret = IRQ_NONE;
127
128 if (mpc83xx_change_state())
129 ret = IRQ_HANDLED;
130
131 if (event) {
132 out_be32(&pmc_regs->event, event);
133 ret = IRQ_HANDLED;
134 }
135
136 return ret;
137}
138
139static int mpc83xx_suspend_enter(suspend_state_t state)
140{
141 int ret = -EAGAIN;
142
143 /* Don't go to sleep if there's a race where pci_pm_state changes
144 * between the agent thread checking it and the PM code disabling
145 * interrupts.
146 */
147 if (wake_from_pci) {
148 if (pci_pm_state != (deep_sleeping ? 3 : 2))
149 goto out;
150
151 out_be32(&pmc_regs->config1,
152 in_be32(&pmc_regs->config1) | PMCCR1_PME_EN);
153 }
154
155 /* Put the system into low-power mode and the RAM
156 * into self-refresh mode once the core goes to
157 * sleep.
158 */
159
160 out_be32(&pmc_regs->config, PMCCR_SLPEN | PMCCR_DLPEN);
161
162 /* If it has deep sleep (i.e. it's an 831x or compatible),
163 * disable power to the core upon entering sleep mode. This will
164 * require going through the boot firmware upon a wakeup event.
165 */
166
167 if (deep_sleeping) {
168 out_be32(&pmc_regs->mask, PMCER_ALL);
169
170 out_be32(&pmc_regs->config1,
171 in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF);
172
173 enable_kernel_fp();
174
175 mpc83xx_enter_deep_sleep(immrbase);
176
177 out_be32(&pmc_regs->config1,
178 in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
179
180 out_be32(&pmc_regs->mask, PMCER_PMCI);
181 } else {
182 out_be32(&pmc_regs->mask, PMCER_PMCI);
183
184 mpc6xx_enter_standby();
185 }
186
187 ret = 0;
188
189out:
190 out_be32(&pmc_regs->config1,
191 in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN);
192
193 return ret;
194}
195
196static void mpc83xx_suspend_finish(void)
197{
198 deep_sleeping = 0;
199}
200
201static int mpc83xx_suspend_valid(suspend_state_t state)
202{
203 return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM;
204}
205
206static int mpc83xx_suspend_begin(suspend_state_t state)
207{
208 switch (state) {
209 case PM_SUSPEND_STANDBY:
210 deep_sleeping = 0;
211 return 0;
212
213 case PM_SUSPEND_MEM:
214 if (has_deep_sleep)
215 deep_sleeping = 1;
216
217 return 0;
218
219 default:
220 return -EINVAL;
221 }
222}
223
224static int agent_thread_fn(void *data)
225{
226 while (1) {
227 wait_event_interruptible(agent_wq, pci_pm_state >= 2);
228 try_to_freeze();
229
230 if (signal_pending(current) || pci_pm_state < 2)
231 continue;
232
233 /* With a preemptible kernel (or SMP), this could race with
234 * a userspace-driven suspend request. It's probably best
235 * to avoid mixing the two with such a configuration (or
236 * else fix it by adding a mutex to state_store that we can
237 * synchronize with).
238 */
239
240 wake_from_pci = 1;
241
242 pm_suspend(pci_pm_state == 3 ? PM_SUSPEND_MEM :
243 PM_SUSPEND_STANDBY);
244
245 wake_from_pci = 0;
246 }
247
248 return 0;
249}
250
251static void mpc83xx_set_agent(void)
252{
253 out_be32(&pmc_regs->config1, PMCCR1_USE_STATE);
254 out_be32(&pmc_regs->mask, PMCER_PMCI);
255
256 kthread_run(agent_thread_fn, NULL, "PCI power mgt");
257}
258
259static int mpc83xx_is_pci_agent(void)
260{
261 struct mpc83xx_rcw __iomem *rcw_regs;
262 int ret;
263
264 rcw_regs = ioremap(get_immrbase() + IMMR_RCW_OFFSET,
265 sizeof(struct mpc83xx_rcw));
266
267 if (!rcw_regs)
268 return -ENOMEM;
269
270 ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST);
271
272 iounmap(rcw_regs);
273 return ret;
274}
275
276static struct platform_suspend_ops mpc83xx_suspend_ops = {
277 .valid = mpc83xx_suspend_valid,
278 .begin = mpc83xx_suspend_begin,
279 .enter = mpc83xx_suspend_enter,
280 .finish = mpc83xx_suspend_finish,
281};
282
283static int pmc_probe(struct of_device *ofdev,
284 const struct of_device_id *match)
285{
286 struct device_node *np = ofdev->node;
287 struct resource res;
288 struct pmc_type *type = match->data;
289 int ret = 0;
290
291 if (!of_device_is_available(np))
292 return -ENODEV;
293
294 has_deep_sleep = type->has_deep_sleep;
295 immrbase = get_immrbase();
296 pmc_dev = ofdev;
297
298 is_pci_agent = mpc83xx_is_pci_agent();
299 if (is_pci_agent < 0)
300 return is_pci_agent;
301
302 ret = of_address_to_resource(np, 0, &res);
303 if (ret)
304 return -ENODEV;
305
306 pmc_irq = irq_of_parse_and_map(np, 0);
307 if (pmc_irq != NO_IRQ) {
308 ret = request_irq(pmc_irq, pmc_irq_handler, IRQF_SHARED,
309 "pmc", ofdev);
310
311 if (ret)
312 return -EBUSY;
313 }
314
315 pmc_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
316
317 if (!pmc_regs) {
318 ret = -ENOMEM;
319 goto out;
320 }
321
322 ret = of_address_to_resource(np, 1, &res);
323 if (ret) {
324 ret = -ENODEV;
325 goto out_pmc;
326 }
327
328 clock_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
329
330 if (!clock_regs) {
331 ret = -ENOMEM;
332 goto out_pmc;
333 }
334
335 if (is_pci_agent)
336 mpc83xx_set_agent();
337
338 suspend_set_ops(&mpc83xx_suspend_ops);
339 return 0;
340
341out_pmc:
342 iounmap(pmc_regs);
343out:
344 if (pmc_irq != NO_IRQ)
345 free_irq(pmc_irq, ofdev);
346
347 return ret;
348}
349
350static int pmc_remove(struct of_device *ofdev)
351{
352 return -EPERM;
353};
354
355static struct pmc_type pmc_types[] = {
356 {
357 .has_deep_sleep = 1,
358 },
359 {
360 .has_deep_sleep = 0,
361 }
362};
363
364static struct of_device_id pmc_match[] = {
365 {
366 .compatible = "fsl,mpc8313-pmc",
367 .data = &pmc_types[0],
368 },
369 {
370 .compatible = "fsl,mpc8349-pmc",
371 .data = &pmc_types[1],
372 },
373 {}
374};
375
376static struct of_platform_driver pmc_driver = {
377 .name = "mpc83xx-pmc",
378 .match_table = pmc_match,
379 .probe = pmc_probe,
380 .remove = pmc_remove
381};
382
383static int pmc_init(void)
384{
385 return of_register_platform_driver(&pmc_driver);
386}
387
388module_init(pmc_init);
diff --git a/arch/powerpc/platforms/83xx/usb.c b/arch/powerpc/platforms/83xx/usb.c
index 64bcf0a33c71..cc99c280aad9 100644
--- a/arch/powerpc/platforms/83xx/usb.c
+++ b/arch/powerpc/platforms/83xx/usb.c
@@ -137,15 +137,21 @@ int mpc831x_usb_cfg(void)
137 137
138 /* Configure pin mux for ULPI. There is no pin mux for UTMI */ 138 /* Configure pin mux for ULPI. There is no pin mux for UTMI */
139 if (prop && !strcmp(prop, "ulpi")) { 139 if (prop && !strcmp(prop, "ulpi")) {
140 temp = in_be32(immap + MPC83XX_SICRL_OFFS); 140 if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) {
141 temp &= ~MPC831X_SICRL_USB_MASK; 141 clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
142 temp |= MPC831X_SICRL_USB_ULPI; 142 MPC8315_SICRL_USB_MASK,
143 out_be32(immap + MPC83XX_SICRL_OFFS, temp); 143 MPC8315_SICRL_USB_ULPI);
144 144 clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
145 temp = in_be32(immap + MPC83XX_SICRH_OFFS); 145 MPC8315_SICRH_USB_MASK,
146 temp &= ~MPC831X_SICRH_USB_MASK; 146 MPC8315_SICRH_USB_ULPI);
147 temp |= MPC831X_SICRH_USB_ULPI; 147 } else {
148 out_be32(immap + MPC83XX_SICRH_OFFS, temp); 148 clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
149 MPC831X_SICRL_USB_MASK,
150 MPC831X_SICRL_USB_ULPI);
151 clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
152 MPC831X_SICRH_USB_MASK,
153 MPC831X_SICRH_USB_ULPI);
154 }
149 } 155 }
150 156
151 iounmap(immap); 157 iounmap(immap);
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index cebea5cadbc1..291675b0097a 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -2,8 +2,8 @@ menuconfig MPC85xx
2 bool "Machine Type" 2 bool "Machine Type"
3 depends on PPC_85xx 3 depends on PPC_85xx
4 select PPC_UDBG_16550 4 select PPC_UDBG_16550
5 select PPC_INDIRECT_PCI if PCI
6 select MPIC 5 select MPIC
6 select PPC_PCI_CHOICE
7 select FSL_PCI if PCI 7 select FSL_PCI if PCI
8 select SERIAL_8250_SHARE_IRQ if SERIAL_8250 8 select SERIAL_8250_SHARE_IRQ if SERIAL_8250
9 default y 9 default y
@@ -86,7 +86,6 @@ config TQM8548
86 help 86 help
87 This option enables support for the TQ Components TQM8548 board. 87 This option enables support for the TQ Components TQM8548 board.
88 select DEFAULT_UIMAGE 88 select DEFAULT_UIMAGE
89 select PPC_CPM_NEW_BINDING
90 select TQM85xx 89 select TQM85xx
91 90
92config TQM8555 91config TQM8555
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 25f41cd2d33a..00c535806647 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -115,7 +115,6 @@ void __init mpc85xx_ds_pic_init(void)
115 115
116#ifdef CONFIG_PCI 116#ifdef CONFIG_PCI
117static int primary_phb_addr; 117static int primary_phb_addr;
118extern int uses_fsl_uli_m1575;
119extern int uli_exclude_device(struct pci_controller *hose, 118extern int uli_exclude_device(struct pci_controller *hose,
120 u_char bus, u_char devfn); 119 u_char bus, u_char devfn);
121 120
@@ -161,7 +160,6 @@ static void __init mpc85xx_ds_setup_arch(void)
161 } 160 }
162 } 161 }
163 162
164 uses_fsl_uli_m1575 = 1;
165 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 163 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
166#endif 164#endif
167 165
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 80a81e02bb55..9355a5269431 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -27,6 +27,7 @@ config SBC8641D
27config MPC8610_HPCD 27config MPC8610_HPCD
28 bool "Freescale MPC8610 HPCD" 28 bool "Freescale MPC8610 HPCD"
29 select DEFAULT_UIMAGE 29 select DEFAULT_UIMAGE
30 select FSL_ULI1575
30 help 31 help
31 This option enables support for the MPC8610 HPCD board. 32 This option enables support for the MPC8610 HPCD board.
32 33
@@ -34,6 +35,7 @@ endif
34 35
35config MPC8641 36config MPC8641
36 bool 37 bool
38 select PPC_PCI_CHOICE
37 select FSL_PCI if PCI 39 select FSL_PCI if PCI
38 select PPC_UDBG_16550 40 select PPC_UDBG_16550
39 select MPIC 41 select MPIC
@@ -41,6 +43,7 @@ config MPC8641
41 43
42config MPC8610 44config MPC8610
43 bool 45 bool
46 select PPC_PCI_CHOICE
44 select FSL_PCI if PCI 47 select FSL_PCI if PCI
45 select PPC_UDBG_16550 48 select PPC_UDBG_16550
46 select MPIC 49 select MPIC
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 30725302884a..5eedb710896e 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -58,93 +58,6 @@ static int __init mpc8610_declare_of_platform_devices(void)
58} 58}
59machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices); 59machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
60 60
61#ifdef CONFIG_PCI
62static void __devinit quirk_uli1575(struct pci_dev *dev)
63{
64 u32 temp32;
65
66 /* Disable INTx */
67 pci_read_config_dword(dev, 0x48, &temp32);
68 pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
69
70 /* Enable sideband interrupt */
71 pci_read_config_dword(dev, 0x90, &temp32);
72 pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
73}
74
75static void __devinit quirk_uli5288(struct pci_dev *dev)
76{
77 unsigned char c;
78 unsigned short temp;
79
80 /* Interrupt Disable, Needed when SATA disabled */
81 pci_read_config_word(dev, PCI_COMMAND, &temp);
82 temp |= 1<<10;
83 pci_write_config_word(dev, PCI_COMMAND, temp);
84
85 pci_read_config_byte(dev, 0x83, &c);
86 c |= 0x80;
87 pci_write_config_byte(dev, 0x83, c);
88
89 pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
90 pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
91
92 pci_read_config_byte(dev, 0x83, &c);
93 c &= 0x7f;
94 pci_write_config_byte(dev, 0x83, c);
95}
96
97/*
98 * Since 8259PIC was disabled on the board, the IDE device can not
99 * use the legacy IRQ, we need to let the IDE device work under
100 * native mode and use the interrupt line like other PCI devices.
101 * IRQ14 is a sideband interrupt from IDE device to CPU and we use this
102 * as the interrupt for IDE device.
103 */
104static void __devinit quirk_uli5229(struct pci_dev *dev)
105{
106 unsigned char c;
107
108 pci_read_config_byte(dev, 0x4b, &c);
109 c |= 0x10;
110 pci_write_config_byte(dev, 0x4b, c);
111}
112
113/*
114 * SATA interrupt pin bug fix
115 * There's a chip bug for 5288, The interrupt pin should be 2,
116 * not the read only value 1, So it use INTB#, not INTA# which
117 * actually used by the IDE device 5229.
118 * As of this bug, during the PCI initialization, 5288 read the
119 * irq of IDE device from the device tree, this function fix this
120 * bug by re-assigning a correct irq to 5288.
121 *
122 */
123static void __devinit final_uli5288(struct pci_dev *dev)
124{
125 struct pci_controller *hose = pci_bus_to_host(dev->bus);
126 struct device_node *hosenode = hose ? hose->dn : NULL;
127 struct of_irq oirq;
128 int virq, pin = 2;
129 u32 laddr[3];
130
131 if (!hosenode)
132 return;
133
134 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
135 laddr[1] = laddr[2] = 0;
136 of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
137 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
138 oirq.size);
139 dev->irq = virq;
140}
141
142DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
143DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
144DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
146#endif /* CONFIG_PCI */
147
148#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 61#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
149 62
150static u32 get_busfreq(void) 63static u32 get_busfreq(void)
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 7916599c9126..f712d9c0991b 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -45,7 +45,6 @@
45#endif 45#endif
46 46
47#ifdef CONFIG_PCI 47#ifdef CONFIG_PCI
48extern int uses_fsl_uli_m1575;
49extern int uli_exclude_device(struct pci_controller *hose, 48extern int uli_exclude_device(struct pci_controller *hose,
50 u_char bus, u_char devfn); 49 u_char bus, u_char devfn);
51 50
@@ -87,7 +86,6 @@ mpc86xx_hpcn_setup_arch(void)
87 fsl_add_bridge(np, 0); 86 fsl_add_bridge(np, 0);
88 } 87 }
89 88
90 uses_fsl_uli_m1575 = 1;
91 ppc_md.pci_exclude_device = mpc86xx_exclude_device; 89 ppc_md.pci_exclude_device = mpc86xx_exclude_device;
92 90
93#endif 91#endif
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 690c1f46e698..1d0968775c0a 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -253,17 +253,13 @@ config CPM2
253 depends on MPC85xx || 8260 253 depends on MPC85xx || 8260
254 select CPM 254 select CPM
255 select PPC_LIB_RHEAP 255 select PPC_LIB_RHEAP
256 select PPC_PCI_CHOICE
256 help 257 help
257 The CPM2 (Communications Processor Module) is a coprocessor on 258 The CPM2 (Communications Processor Module) is a coprocessor on
258 embedded CPUs made by Freescale. Selecting this option means that 259 embedded CPUs made by Freescale. Selecting this option means that
259 you wish to build a kernel for a machine with a CPM2 coprocessor 260 you wish to build a kernel for a machine with a CPM2 coprocessor
260 on it (826x, 827x, 8560). 261 on it (826x, 827x, 8560).
261 262
262config PPC_CPM_NEW_BINDING
263 bool
264 depends on CPM1 || CPM2
265 default y
266
267config AXON_RAM 263config AXON_RAM
268 tristate "Axon DDR2 memory device driver" 264 tristate "Axon DDR2 memory device driver"
269 depends on PPC_IBM_CELL_BLADE 265 depends on PPC_IBM_CELL_BLADE
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 5bc4b611ff88..7f6512733862 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -42,12 +42,14 @@ config 40x
42 select PPC_DCR_NATIVE 42 select PPC_DCR_NATIVE
43 select PPC_UDBG_16550 43 select PPC_UDBG_16550
44 select 4xx_SOC 44 select 4xx_SOC
45 select PPC_PCI_CHOICE
45 46
46config 44x 47config 44x
47 bool "AMCC 44x" 48 bool "AMCC 44x"
48 select PPC_DCR_NATIVE 49 select PPC_DCR_NATIVE
49 select PPC_UDBG_16550 50 select PPC_UDBG_16550
50 select 4xx_SOC 51 select 4xx_SOC
52 select PPC_PCI_CHOICE
51 53
52config E200 54config E200
53 bool "Freescale e200" 55 bool "Freescale e200"
@@ -84,9 +86,6 @@ config TUNE_CELL
84 machines. When building a kernel that is supposed to run only 86 machines. When building a kernel that is supposed to run only
85 on Cell, you should also select the POWER4_ONLY option. 87 on Cell, you should also select the POWER4_ONLY option.
86 88
87config 6xx
88 bool
89
90# this is temp to handle compat with arch=ppc 89# this is temp to handle compat with arch=ppc
91config 8xx 90config 8xx
92 bool 91 bool
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 3959fcfe731c..c14d7d8d96c8 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -83,6 +83,22 @@ config CBE_RAS
83 depends on PPC_CELL_NATIVE 83 depends on PPC_CELL_NATIVE
84 default y 84 default y
85 85
86config PPC_IBM_CELL_RESETBUTTON
87 bool "IBM Cell Blade Pinhole reset button"
88 depends on CBE_RAS && PPC_IBM_CELL_BLADE
89 default y
90 help
91 Support Pinhole Resetbutton on IBM Cell blades.
92 This adds a method to trigger system reset via front panel pinhole button.
93
94config PPC_IBM_CELL_POWERBUTTON
95 tristate "IBM Cell Blade power button"
96 depends on PPC_IBM_CELL_BLADE && PPC_PMI && INPUT_EVDEV
97 default y
98 help
99 Support Powerbutton on IBM Cell blades.
100 This will enable the powerbutton as an input device.
101
86config CBE_THERM 102config CBE_THERM
87 tristate "CBE thermal support" 103 tristate "CBE thermal support"
88 default m 104 default m
@@ -107,6 +123,15 @@ config CBE_CPUFREQ_PMI
107 processor will not only be able to run at lower speed, 123 processor will not only be able to run at lower speed,
108 but also at lower core voltage. 124 but also at lower core voltage.
109 125
126config CBE_CPUFREQ_SPU_GOVERNOR
127 tristate "CBE frequency scaling based on SPU usage"
128 depends on SPU_FS && CPU_FREQ
129 default m
130 help
131 This governor checks for spu usage to adjust the cpu frequency.
132 If no spu is running on a given cpu, that cpu will be throttled to
133 the minimal possible frequency.
134
110endmenu 135endmenu
111 136
112config OPROFILE_CELL 137config OPROFILE_CELL
diff --git a/arch/powerpc/platforms/cell/Makefile b/arch/powerpc/platforms/cell/Makefile
index c2a7e4e5ddf9..7fd830872c43 100644
--- a/arch/powerpc/platforms/cell/Makefile
+++ b/arch/powerpc/platforms/cell/Makefile
@@ -8,6 +8,9 @@ obj-$(CONFIG_CBE_THERM) += cbe_thermal.o
8obj-$(CONFIG_CBE_CPUFREQ_PMI) += cbe_cpufreq_pmi.o 8obj-$(CONFIG_CBE_CPUFREQ_PMI) += cbe_cpufreq_pmi.o
9obj-$(CONFIG_CBE_CPUFREQ) += cbe-cpufreq.o 9obj-$(CONFIG_CBE_CPUFREQ) += cbe-cpufreq.o
10cbe-cpufreq-y += cbe_cpufreq_pervasive.o cbe_cpufreq.o 10cbe-cpufreq-y += cbe_cpufreq_pervasive.o cbe_cpufreq.o
11obj-$(CONFIG_CBE_CPUFREQ_SPU_GOVERNOR) += cpufreq_spudemand.o
12
13obj-$(CONFIG_PPC_IBM_CELL_POWERBUTTON) += cbe_powerbutton.o
11 14
12ifeq ($(CONFIG_SMP),y) 15ifeq ($(CONFIG_SMP),y)
13obj-$(CONFIG_PPC_CELL_NATIVE) += smp.o 16obj-$(CONFIG_PPC_CELL_NATIVE) += smp.o
diff --git a/arch/powerpc/platforms/cell/cbe_powerbutton.c b/arch/powerpc/platforms/cell/cbe_powerbutton.c
new file mode 100644
index 000000000000..dcddaa5fcb66
--- /dev/null
+++ b/arch/powerpc/platforms/cell/cbe_powerbutton.c
@@ -0,0 +1,117 @@
1/*
2 * driver for powerbutton on IBM cell blades
3 *
4 * (C) Copyright IBM Corp. 2005-2008
5 *
6 * Author: Christian Krafft <krafft@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/input.h>
24#include <linux/platform_device.h>
25#include <asm/pmi.h>
26#include <asm/prom.h>
27
28static struct input_dev *button_dev;
29static struct platform_device *button_pdev;
30
31static void cbe_powerbutton_handle_pmi(pmi_message_t pmi_msg)
32{
33 BUG_ON(pmi_msg.type != PMI_TYPE_POWER_BUTTON);
34
35 input_report_key(button_dev, KEY_POWER, 1);
36 input_sync(button_dev);
37 input_report_key(button_dev, KEY_POWER, 0);
38 input_sync(button_dev);
39}
40
41static struct pmi_handler cbe_pmi_handler = {
42 .type = PMI_TYPE_POWER_BUTTON,
43 .handle_pmi_message = cbe_powerbutton_handle_pmi,
44};
45
46static int __init cbe_powerbutton_init(void)
47{
48 int ret = 0;
49 struct input_dev *dev;
50
51 if (!machine_is_compatible("IBM,CBPLUS-1.0")) {
52 printk(KERN_ERR "%s: Not a cell blade.\n", __func__);
53 ret = -ENODEV;
54 goto out;
55 }
56
57 dev = input_allocate_device();
58 if (!dev) {
59 ret = -ENOMEM;
60 printk(KERN_ERR "%s: Not enough memory.\n", __func__);
61 goto out;
62 }
63
64 set_bit(EV_KEY, dev->evbit);
65 set_bit(KEY_POWER, dev->keybit);
66
67 dev->name = "Power Button";
68 dev->id.bustype = BUS_HOST;
69
70 /* this makes the button look like an acpi power button
71 * no clue whether anyone relies on that though */
72 dev->id.product = 0x02;
73 dev->phys = "LNXPWRBN/button/input0";
74
75 button_pdev = platform_device_register_simple("power_button", 0, NULL, 0);
76 if (IS_ERR(button_pdev)) {
77 ret = PTR_ERR(button_pdev);
78 goto out_free_input;
79 }
80
81 dev->dev.parent = &button_pdev->dev;
82 ret = input_register_device(dev);
83 if (ret) {
84 printk(KERN_ERR "%s: Failed to register device\n", __func__);
85 goto out_free_pdev;
86 }
87
88 button_dev = dev;
89
90 ret = pmi_register_handler(&cbe_pmi_handler);
91 if (ret) {
92 printk(KERN_ERR "%s: Failed to register with pmi.\n", __func__);
93 goto out_free_pdev;
94 }
95
96 goto out;
97
98out_free_pdev:
99 platform_device_unregister(button_pdev);
100out_free_input:
101 input_free_device(dev);
102out:
103 return ret;
104}
105
106static void __exit cbe_powerbutton_exit(void)
107{
108 pmi_unregister_handler(&cbe_pmi_handler);
109 platform_device_unregister(button_pdev);
110 input_free_device(button_dev);
111}
112
113module_init(cbe_powerbutton_init);
114module_exit(cbe_powerbutton_exit);
115
116MODULE_LICENSE("GPL");
117MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>");
diff --git a/arch/powerpc/platforms/cell/cpufreq_spudemand.c b/arch/powerpc/platforms/cell/cpufreq_spudemand.c
new file mode 100644
index 000000000000..a3c6c01bd6db
--- /dev/null
+++ b/arch/powerpc/platforms/cell/cpufreq_spudemand.c
@@ -0,0 +1,184 @@
1/*
2 * spu aware cpufreq governor for the cell processor
3 *
4 * © Copyright IBM Corporation 2006-2008
5 *
6 * Author: Christian Krafft <krafft@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/cpufreq.h>
24#include <linux/sched.h>
25#include <linux/timer.h>
26#include <linux/workqueue.h>
27#include <asm/atomic.h>
28#include <asm/machdep.h>
29#include <asm/spu.h>
30
31#define POLL_TIME 100000 /* in µs */
32#define EXP 753 /* exp(-1) in fixed-point */
33
34struct spu_gov_info_struct {
35 unsigned long busy_spus; /* fixed-point */
36 struct cpufreq_policy *policy;
37 struct delayed_work work;
38 unsigned int poll_int; /* µs */
39};
40static DEFINE_PER_CPU(struct spu_gov_info_struct, spu_gov_info);
41
42static struct workqueue_struct *kspugov_wq;
43
44static int calc_freq(struct spu_gov_info_struct *info)
45{
46 int cpu;
47 int busy_spus;
48
49 cpu = info->policy->cpu;
50 busy_spus = atomic_read(&cbe_spu_info[cpu_to_node(cpu)].busy_spus);
51
52 CALC_LOAD(info->busy_spus, EXP, busy_spus * FIXED_1);
53 pr_debug("cpu %d: busy_spus=%d, info->busy_spus=%ld\n",
54 cpu, busy_spus, info->busy_spus);
55
56 return info->policy->max * info->busy_spus / FIXED_1;
57}
58
59static void spu_gov_work(struct work_struct *work)
60{
61 struct spu_gov_info_struct *info;
62 int delay;
63 unsigned long target_freq;
64
65 info = container_of(work, struct spu_gov_info_struct, work.work);
66
67 /* after cancel_delayed_work_sync we unset info->policy */
68 BUG_ON(info->policy == NULL);
69
70 target_freq = calc_freq(info);
71 __cpufreq_driver_target(info->policy, target_freq, CPUFREQ_RELATION_H);
72
73 delay = usecs_to_jiffies(info->poll_int);
74 queue_delayed_work_on(info->policy->cpu, kspugov_wq, &info->work, delay);
75}
76
77static void spu_gov_init_work(struct spu_gov_info_struct *info)
78{
79 int delay = usecs_to_jiffies(info->poll_int);
80 INIT_DELAYED_WORK_DEFERRABLE(&info->work, spu_gov_work);
81 queue_delayed_work_on(info->policy->cpu, kspugov_wq, &info->work, delay);
82}
83
84static void spu_gov_cancel_work(struct spu_gov_info_struct *info)
85{
86 cancel_delayed_work_sync(&info->work);
87}
88
89static int spu_gov_govern(struct cpufreq_policy *policy, unsigned int event)
90{
91 unsigned int cpu = policy->cpu;
92 struct spu_gov_info_struct *info, *affected_info;
93 int i;
94 int ret = 0;
95
96 info = &per_cpu(spu_gov_info, cpu);
97
98 switch (event) {
99 case CPUFREQ_GOV_START:
100 if (!cpu_online(cpu)) {
101 printk(KERN_ERR "cpu %d is not online\n", cpu);
102 ret = -EINVAL;
103 break;
104 }
105
106 if (!policy->cur) {
107 printk(KERN_ERR "no cpu specified in policy\n");
108 ret = -EINVAL;
109 break;
110 }
111
112 /* initialize spu_gov_info for all affected cpus */
113 for_each_cpu_mask(i, policy->cpus) {
114 affected_info = &per_cpu(spu_gov_info, i);
115 affected_info->policy = policy;
116 }
117
118 info->poll_int = POLL_TIME;
119
120 /* setup timer */
121 spu_gov_init_work(info);
122
123 break;
124
125 case CPUFREQ_GOV_STOP:
126 /* cancel timer */
127 spu_gov_cancel_work(info);
128
129 /* clean spu_gov_info for all affected cpus */
130 for_each_cpu_mask (i, policy->cpus) {
131 info = &per_cpu(spu_gov_info, i);
132 info->policy = NULL;
133 }
134
135 break;
136 }
137
138 return ret;
139}
140
141static struct cpufreq_governor spu_governor = {
142 .name = "spudemand",
143 .governor = spu_gov_govern,
144 .owner = THIS_MODULE,
145};
146
147/*
148 * module init and destoy
149 */
150
151static int __init spu_gov_init(void)
152{
153 int ret;
154
155 kspugov_wq = create_workqueue("kspugov");
156 if (!kspugov_wq) {
157 printk(KERN_ERR "creation of kspugov failed\n");
158 ret = -EFAULT;
159 goto out;
160 }
161
162 ret = cpufreq_register_governor(&spu_governor);
163 if (ret) {
164 printk(KERN_ERR "registration of governor failed\n");
165 destroy_workqueue(kspugov_wq);
166 goto out;
167 }
168out:
169 return ret;
170}
171
172static void __exit spu_gov_exit(void)
173{
174 cpufreq_unregister_governor(&spu_governor);
175 destroy_workqueue(kspugov_wq);
176}
177
178
179module_init(spu_gov_init);
180module_exit(spu_gov_exit);
181
182MODULE_LICENSE("GPL");
183MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>");
184
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index eeacb3a52ca1..208005ca262c 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -173,7 +173,8 @@ static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte,
173} 173}
174 174
175static void tce_build_cell(struct iommu_table *tbl, long index, long npages, 175static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
176 unsigned long uaddr, enum dma_data_direction direction) 176 unsigned long uaddr, enum dma_data_direction direction,
177 struct dma_attrs *attrs)
177{ 178{
178 int i; 179 int i;
179 unsigned long *io_pte, base_pte; 180 unsigned long *io_pte, base_pte;
@@ -198,6 +199,8 @@ static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
198 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | 199 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW |
199 (window->ioid & IOPTE_IOID_Mask); 200 (window->ioid & IOPTE_IOID_Mask);
200#endif 201#endif
202 if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)))
203 base_pte &= ~IOPTE_SO_RW;
201 204
202 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 205 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
203 206
@@ -519,7 +522,7 @@ cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
519 522
520 __set_bit(0, window->table.it_map); 523 __set_bit(0, window->table.it_map);
521 tce_build_cell(&window->table, window->table.it_offset, 1, 524 tce_build_cell(&window->table, window->table.it_offset, 1,
522 (unsigned long)iommu->pad_page, DMA_TO_DEVICE); 525 (unsigned long)iommu->pad_page, DMA_TO_DEVICE, NULL);
523 window->table.it_hint = window->table.it_blocksize; 526 window->table.it_hint = window->table.it_blocksize;
524 527
525 return window; 528 return window;
@@ -538,7 +541,9 @@ static struct cbe_iommu *cell_iommu_for_node(int nid)
538static unsigned long cell_dma_direct_offset; 541static unsigned long cell_dma_direct_offset;
539 542
540static unsigned long dma_iommu_fixed_base; 543static unsigned long dma_iommu_fixed_base;
541struct dma_mapping_ops dma_iommu_fixed_ops; 544
545/* iommu_fixed_is_weak is set if booted with iommu_fixed=weak */
546static int iommu_fixed_is_weak;
542 547
543static struct iommu_table *cell_get_iommu_table(struct device *dev) 548static struct iommu_table *cell_get_iommu_table(struct device *dev)
544{ 549{
@@ -562,6 +567,98 @@ static struct iommu_table *cell_get_iommu_table(struct device *dev)
562 return &window->table; 567 return &window->table;
563} 568}
564 569
570/* A coherent allocation implies strong ordering */
571
572static void *dma_fixed_alloc_coherent(struct device *dev, size_t size,
573 dma_addr_t *dma_handle, gfp_t flag)
574{
575 if (iommu_fixed_is_weak)
576 return iommu_alloc_coherent(dev, cell_get_iommu_table(dev),
577 size, dma_handle,
578 device_to_mask(dev), flag,
579 dev->archdata.numa_node);
580 else
581 return dma_direct_ops.alloc_coherent(dev, size, dma_handle,
582 flag);
583}
584
585static void dma_fixed_free_coherent(struct device *dev, size_t size,
586 void *vaddr, dma_addr_t dma_handle)
587{
588 if (iommu_fixed_is_weak)
589 iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr,
590 dma_handle);
591 else
592 dma_direct_ops.free_coherent(dev, size, vaddr, dma_handle);
593}
594
595static dma_addr_t dma_fixed_map_single(struct device *dev, void *ptr,
596 size_t size,
597 enum dma_data_direction direction,
598 struct dma_attrs *attrs)
599{
600 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
601 return dma_direct_ops.map_single(dev, ptr, size, direction,
602 attrs);
603 else
604 return iommu_map_single(dev, cell_get_iommu_table(dev), ptr,
605 size, device_to_mask(dev), direction,
606 attrs);
607}
608
609static void dma_fixed_unmap_single(struct device *dev, dma_addr_t dma_addr,
610 size_t size,
611 enum dma_data_direction direction,
612 struct dma_attrs *attrs)
613{
614 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
615 dma_direct_ops.unmap_single(dev, dma_addr, size, direction,
616 attrs);
617 else
618 iommu_unmap_single(cell_get_iommu_table(dev), dma_addr, size,
619 direction, attrs);
620}
621
622static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg,
623 int nents, enum dma_data_direction direction,
624 struct dma_attrs *attrs)
625{
626 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
627 return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs);
628 else
629 return iommu_map_sg(dev, cell_get_iommu_table(dev), sg, nents,
630 device_to_mask(dev), direction, attrs);
631}
632
633static void dma_fixed_unmap_sg(struct device *dev, struct scatterlist *sg,
634 int nents, enum dma_data_direction direction,
635 struct dma_attrs *attrs)
636{
637 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
638 dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs);
639 else
640 iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents, direction,
641 attrs);
642}
643
644static int dma_fixed_dma_supported(struct device *dev, u64 mask)
645{
646 return mask == DMA_64BIT_MASK;
647}
648
649static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask);
650
651struct dma_mapping_ops dma_iommu_fixed_ops = {
652 .alloc_coherent = dma_fixed_alloc_coherent,
653 .free_coherent = dma_fixed_free_coherent,
654 .map_single = dma_fixed_map_single,
655 .unmap_single = dma_fixed_unmap_single,
656 .map_sg = dma_fixed_map_sg,
657 .unmap_sg = dma_fixed_unmap_sg,
658 .dma_supported = dma_fixed_dma_supported,
659 .set_dma_mask = dma_set_mask_and_switch,
660};
661
565static void cell_dma_dev_setup_fixed(struct device *dev); 662static void cell_dma_dev_setup_fixed(struct device *dev);
566 663
567static void cell_dma_dev_setup(struct device *dev) 664static void cell_dma_dev_setup(struct device *dev)
@@ -918,9 +1015,16 @@ static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
918 1015
919 pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase); 1016 pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
920 1017
921 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW 1018 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M
922 | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask); 1019 | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask);
923 1020
1021 if (iommu_fixed_is_weak)
1022 pr_info("IOMMU: Using weak ordering for fixed mapping\n");
1023 else {
1024 pr_info("IOMMU: Using strong ordering for fixed mapping\n");
1025 base_pte |= IOPTE_SO_RW;
1026 }
1027
924 for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) { 1028 for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
925 /* Don't touch the dynamic region */ 1029 /* Don't touch the dynamic region */
926 ioaddr = uaddr + fbase; 1030 ioaddr = uaddr + fbase;
@@ -1036,9 +1140,6 @@ static int __init cell_iommu_fixed_mapping_init(void)
1036 cell_iommu_setup_window(iommu, np, dbase, dsize, 0); 1140 cell_iommu_setup_window(iommu, np, dbase, dsize, 0);
1037 } 1141 }
1038 1142
1039 dma_iommu_fixed_ops = dma_direct_ops;
1040 dma_iommu_fixed_ops.set_dma_mask = dma_set_mask_and_switch;
1041
1042 dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch; 1143 dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch;
1043 set_pci_dma_ops(&dma_iommu_ops); 1144 set_pci_dma_ops(&dma_iommu_ops);
1044 1145
@@ -1052,6 +1153,9 @@ static int __init setup_iommu_fixed(char *str)
1052 if (strcmp(str, "off") == 0) 1153 if (strcmp(str, "off") == 0)
1053 iommu_fixed_disabled = 1; 1154 iommu_fixed_disabled = 1;
1054 1155
1156 else if (strcmp(str, "weak") == 0)
1157 iommu_fixed_is_weak = 1;
1158
1055 return 1; 1159 return 1;
1056} 1160}
1057__setup("iommu_fixed=", setup_iommu_fixed); 1161__setup("iommu_fixed=", setup_iommu_fixed);
diff --git a/arch/powerpc/platforms/cell/pervasive.c b/arch/powerpc/platforms/cell/pervasive.c
index 8a3631ce912b..efdacc829576 100644
--- a/arch/powerpc/platforms/cell/pervasive.c
+++ b/arch/powerpc/platforms/cell/pervasive.c
@@ -38,8 +38,6 @@
38 38
39#include "pervasive.h" 39#include "pervasive.h"
40 40
41static int sysreset_hack;
42
43static void cbe_power_save(void) 41static void cbe_power_save(void)
44{ 42{
45 unsigned long ctrl, thread_switch_control; 43 unsigned long ctrl, thread_switch_control;
@@ -87,9 +85,6 @@ static void cbe_power_save(void)
87 85
88static int cbe_system_reset_exception(struct pt_regs *regs) 86static int cbe_system_reset_exception(struct pt_regs *regs)
89{ 87{
90 int cpu;
91 struct cbe_pmd_regs __iomem *pmd;
92
93 switch (regs->msr & SRR1_WAKEMASK) { 88 switch (regs->msr & SRR1_WAKEMASK) {
94 case SRR1_WAKEEE: 89 case SRR1_WAKEEE:
95 do_IRQ(regs); 90 do_IRQ(regs);
@@ -98,19 +93,7 @@ static int cbe_system_reset_exception(struct pt_regs *regs)
98 timer_interrupt(regs); 93 timer_interrupt(regs);
99 break; 94 break;
100 case SRR1_WAKEMT: 95 case SRR1_WAKEMT:
101 /* 96 return cbe_sysreset_hack();
102 * The BMC can inject user triggered system reset exceptions,
103 * but cannot set the system reset reason in srr1,
104 * so check an extra register here.
105 */
106 if (sysreset_hack && (cpu = smp_processor_id()) == 0) {
107 pmd = cbe_get_cpu_pmd_regs(cpu);
108 if (in_be64(&pmd->ras_esc_0) & 0xffff) {
109 out_be64(&pmd->ras_esc_0, 0);
110 return 0;
111 }
112 }
113 break;
114#ifdef CONFIG_CBE_RAS 97#ifdef CONFIG_CBE_RAS
115 case SRR1_WAKESYSERR: 98 case SRR1_WAKESYSERR:
116 cbe_system_error_exception(regs); 99 cbe_system_error_exception(regs);
@@ -134,8 +117,6 @@ void __init cbe_pervasive_init(void)
134 if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO)) 117 if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
135 return; 118 return;
136 119
137 sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0");
138
139 for_each_possible_cpu(cpu) { 120 for_each_possible_cpu(cpu) {
140 struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu); 121 struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
141 if (!regs) 122 if (!regs)
@@ -144,12 +125,6 @@ void __init cbe_pervasive_init(void)
144 /* Enable Pause(0) control bit */ 125 /* Enable Pause(0) control bit */
145 out_be64(&regs->pmcr, in_be64(&regs->pmcr) | 126 out_be64(&regs->pmcr, in_be64(&regs->pmcr) |
146 CBE_PMD_PAUSE_ZERO_CONTROL); 127 CBE_PMD_PAUSE_ZERO_CONTROL);
147
148 /* Enable JTAG system-reset hack */
149 if (sysreset_hack)
150 out_be32(&regs->fir_mode_reg,
151 in_be32(&regs->fir_mode_reg) |
152 CBE_PMD_FIR_MODE_M8);
153 } 128 }
154 129
155 ppc_md.power_save = cbe_power_save; 130 ppc_md.power_save = cbe_power_save;
diff --git a/arch/powerpc/platforms/cell/pervasive.h b/arch/powerpc/platforms/cell/pervasive.h
index 7b50947f8044..fd4d7b7092b4 100644
--- a/arch/powerpc/platforms/cell/pervasive.h
+++ b/arch/powerpc/platforms/cell/pervasive.h
@@ -30,4 +30,13 @@ extern void cbe_system_error_exception(struct pt_regs *regs);
30extern void cbe_maintenance_exception(struct pt_regs *regs); 30extern void cbe_maintenance_exception(struct pt_regs *regs);
31extern void cbe_thermal_exception(struct pt_regs *regs); 31extern void cbe_thermal_exception(struct pt_regs *regs);
32 32
33#ifdef CONFIG_PPC_IBM_CELL_RESETBUTTON
34extern int cbe_sysreset_hack(void);
35#else
36static inline int cbe_sysreset_hack(void)
37{
38 return 1;
39}
40#endif /* CONFIG_PPC_IBM_CELL_RESETBUTTON */
41
33#endif 42#endif
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c
index 505f9b9bdf0c..2a14b052abcd 100644
--- a/arch/powerpc/platforms/cell/ras.c
+++ b/arch/powerpc/platforms/cell/ras.c
@@ -236,6 +236,52 @@ static struct notifier_block cbe_ptcal_reboot_notifier = {
236 .notifier_call = cbe_ptcal_notify_reboot 236 .notifier_call = cbe_ptcal_notify_reboot
237}; 237};
238 238
239#ifdef CONFIG_PPC_IBM_CELL_RESETBUTTON
240static int sysreset_hack;
241
242static int __init cbe_sysreset_init(void)
243{
244 struct cbe_pmd_regs __iomem *regs;
245
246 sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0");
247 if (!sysreset_hack)
248 return 0;
249
250 regs = cbe_get_cpu_pmd_regs(0);
251 if (!regs)
252 return 0;
253
254 /* Enable JTAG system-reset hack */
255 out_be32(&regs->fir_mode_reg,
256 in_be32(&regs->fir_mode_reg) |
257 CBE_PMD_FIR_MODE_M8);
258
259 return 0;
260}
261device_initcall(cbe_sysreset_init);
262
263int cbe_sysreset_hack(void)
264{
265 struct cbe_pmd_regs __iomem *regs;
266
267 /*
268 * The BMC can inject user triggered system reset exceptions,
269 * but cannot set the system reset reason in srr1,
270 * so check an extra register here.
271 */
272 if (sysreset_hack && (smp_processor_id() == 0)) {
273 regs = cbe_get_cpu_pmd_regs(0);
274 if (!regs)
275 return 0;
276 if (in_be64(&regs->ras_esc_0) & 0x0000ffff) {
277 out_be64(&regs->ras_esc_0, 0);
278 return 0;
279 }
280 }
281 return 1;
282}
283#endif /* CONFIG_PPC_IBM_CELL_RESETBUTTON */
284
239int __init cbe_ptcal_init(void) 285int __init cbe_ptcal_init(void)
240{ 286{
241 int ret; 287 int ret;
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c
index afc9141be63e..ef74a0763ec1 100644
--- a/arch/powerpc/platforms/fsl_uli1575.c
+++ b/arch/powerpc/platforms/fsl_uli1575.c
@@ -51,15 +51,13 @@ u8 uli_pirq_to_irq[8] = {
51 ULI_8259_NONE, /* PIRQH */ 51 ULI_8259_NONE, /* PIRQH */
52}; 52};
53 53
54/* set in board code if you want this quirks to do something */
55int uses_fsl_uli_m1575;
56
57/* Bridge */ 54/* Bridge */
58static void __devinit early_uli5249(struct pci_dev *dev) 55static void __devinit early_uli5249(struct pci_dev *dev)
59{ 56{
60 unsigned char temp; 57 unsigned char temp;
61 58
62 if (!uses_fsl_uli_m1575) 59 if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
60 !machine_is(mpc8572_ds))
63 return; 61 return;
64 62
65 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO | 63 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO |
@@ -82,7 +80,8 @@ static void __devinit quirk_uli1575(struct pci_dev *dev)
82{ 80{
83 int i; 81 int i;
84 82
85 if (!uses_fsl_uli_m1575) 83 if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
84 !machine_is(mpc8572_ds))
86 return; 85 return;
87 86
88 /* 87 /*
@@ -150,7 +149,8 @@ static void __devinit quirk_final_uli1575(struct pci_dev *dev)
150 * IRQ 14: Edge 149 * IRQ 14: Edge
151 * IRQ 15: Edge 150 * IRQ 15: Edge
152 */ 151 */
153 if (!uses_fsl_uli_m1575) 152 if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
153 !machine_is(mpc8572_ds))
154 return; 154 return;
155 155
156 outb(0xfa, 0x4d0); 156 outb(0xfa, 0x4d0);
@@ -176,7 +176,8 @@ static void __devinit quirk_uli5288(struct pci_dev *dev)
176 unsigned char c; 176 unsigned char c;
177 unsigned int d; 177 unsigned int d;
178 178
179 if (!uses_fsl_uli_m1575) 179 if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
180 !machine_is(mpc8572_ds))
180 return; 181 return;
181 182
182 /* read/write lock */ 183 /* read/write lock */
@@ -200,7 +201,8 @@ static void __devinit quirk_uli5229(struct pci_dev *dev)
200{ 201{
201 unsigned short temp; 202 unsigned short temp;
202 203
203 if (!uses_fsl_uli_m1575) 204 if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
205 !machine_is(mpc8572_ds))
204 return; 206 return;
205 207
206 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE | 208 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE |
@@ -221,7 +223,7 @@ static void __devinit quirk_final_uli5249(struct pci_dev *dev)
221 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 223 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
222 if ((bus->resource[i]) && 224 if ((bus->resource[i]) &&
223 (bus->resource[i]->flags & IORESOURCE_MEM)) { 225 (bus->resource[i]->flags & IORESOURCE_MEM)) {
224 dummy = ioremap(bus->resource[i]->start, 0x4); 226 dummy = ioremap(bus->resource[i]->end - 3, 0x4);
225 if (dummy) { 227 if (dummy) {
226 in_8(dummy); 228 in_8(dummy);
227 iounmap(dummy); 229 iounmap(dummy);
@@ -238,6 +240,103 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249); 240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249);
239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575); 241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575);
240 242
243static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev)
244{
245 u32 temp32;
246
247 if (!machine_is(mpc86xx_hpcd))
248 return;
249
250 /* Disable INTx */
251 pci_read_config_dword(dev, 0x48, &temp32);
252 pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
253
254 /* Enable sideband interrupt */
255 pci_read_config_dword(dev, 0x90, &temp32);
256 pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
257}
258
259static void __devinit hpcd_quirk_uli5288(struct pci_dev *dev)
260{
261 unsigned char c;
262 unsigned short temp;
263
264 if (!machine_is(mpc86xx_hpcd))
265 return;
266
267 /* Interrupt Disable, Needed when SATA disabled */
268 pci_read_config_word(dev, PCI_COMMAND, &temp);
269 temp |= 1<<10;
270 pci_write_config_word(dev, PCI_COMMAND, temp);
271
272 pci_read_config_byte(dev, 0x83, &c);
273 c |= 0x80;
274 pci_write_config_byte(dev, 0x83, c);
275
276 pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
277 pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
278
279 pci_read_config_byte(dev, 0x83, &c);
280 c &= 0x7f;
281 pci_write_config_byte(dev, 0x83, c);
282}
283
284/*
285 * Since 8259PIC was disabled on the board, the IDE device can not
286 * use the legacy IRQ, we need to let the IDE device work under
287 * native mode and use the interrupt line like other PCI devices.
288 * IRQ14 is a sideband interrupt from IDE device to CPU and we use this
289 * as the interrupt for IDE device.
290 */
291static void __devinit hpcd_quirk_uli5229(struct pci_dev *dev)
292{
293 unsigned char c;
294
295 if (!machine_is(mpc86xx_hpcd))
296 return;
297
298 pci_read_config_byte(dev, 0x4b, &c);
299 c |= 0x10;
300 pci_write_config_byte(dev, 0x4b, c);
301}
302
303/*
304 * SATA interrupt pin bug fix
305 * There's a chip bug for 5288, The interrupt pin should be 2,
306 * not the read only value 1, So it use INTB#, not INTA# which
307 * actually used by the IDE device 5229.
308 * As of this bug, during the PCI initialization, 5288 read the
309 * irq of IDE device from the device tree, this function fix this
310 * bug by re-assigning a correct irq to 5288.
311 *
312 */
313static void __devinit hpcd_final_uli5288(struct pci_dev *dev)
314{
315 struct pci_controller *hose = pci_bus_to_host(dev->bus);
316 struct device_node *hosenode = hose ? hose->dn : NULL;
317 struct of_irq oirq;
318 int virq, pin = 2;
319 u32 laddr[3];
320
321 if (!machine_is(mpc86xx_hpcd))
322 return;
323
324 if (!hosenode)
325 return;
326
327 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
328 laddr[1] = laddr[2] = 0;
329 of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
330 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
331 oirq.size);
332 dev->irq = virq;
333}
334
335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575);
336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288);
337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229);
338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288);
339
241int uli_exclude_device(struct pci_controller *hose, 340int uli_exclude_device(struct pci_controller *hose,
242 u_char bus, u_char devfn) 341 u_char bus, u_char devfn)
243{ 342{
diff --git a/arch/powerpc/platforms/iseries/Kconfig b/arch/powerpc/platforms/iseries/Kconfig
index 761d9e971fc4..ea3e541ac74f 100644
--- a/arch/powerpc/platforms/iseries/Kconfig
+++ b/arch/powerpc/platforms/iseries/Kconfig
@@ -2,6 +2,7 @@ config PPC_ISERIES
2 bool "IBM Legacy iSeries" 2 bool "IBM Legacy iSeries"
3 depends on PPC_MULTIPLATFORM && PPC64 3 depends on PPC_MULTIPLATFORM && PPC64
4 select PPC_INDIRECT_IO 4 select PPC_INDIRECT_IO
5 select PPC_PCI_CHOICE if EMBEDDED
5 6
6menu "iSeries device drivers" 7menu "iSeries device drivers"
7 depends on PPC_ISERIES 8 depends on PPC_ISERIES
diff --git a/arch/powerpc/platforms/iseries/iommu.c b/arch/powerpc/platforms/iseries/iommu.c
index ab5d8687c3cf..bc818e4e2033 100644
--- a/arch/powerpc/platforms/iseries/iommu.c
+++ b/arch/powerpc/platforms/iseries/iommu.c
@@ -42,7 +42,8 @@
42#include <asm/iseries/iommu.h> 42#include <asm/iseries/iommu.h>
43 43
44static void tce_build_iSeries(struct iommu_table *tbl, long index, long npages, 44static void tce_build_iSeries(struct iommu_table *tbl, long index, long npages,
45 unsigned long uaddr, enum dma_data_direction direction) 45 unsigned long uaddr, enum dma_data_direction direction,
46 struct dma_attrs *attrs)
46{ 47{
47 u64 rc; 48 u64 rc;
48 u64 tce, rpn; 49 u64 tce, rpn;
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index 86967bdd8774..70541b7a5013 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -85,7 +85,8 @@ static int iommu_table_iobmap_inited;
85 85
86static void iobmap_build(struct iommu_table *tbl, long index, 86static void iobmap_build(struct iommu_table *tbl, long index,
87 long npages, unsigned long uaddr, 87 long npages, unsigned long uaddr,
88 enum dma_data_direction direction) 88 enum dma_data_direction direction,
89 struct dma_attrs *attrs)
89{ 90{
90 u32 *ip; 91 u32 *ip;
91 u32 rpn; 92 u32 rpn;
diff --git a/arch/powerpc/platforms/ps3/Kconfig b/arch/powerpc/platforms/ps3/Kconfig
index a5f4e95dfc3d..920cf7a454b1 100644
--- a/arch/powerpc/platforms/ps3/Kconfig
+++ b/arch/powerpc/platforms/ps3/Kconfig
@@ -8,6 +8,7 @@ config PPC_PS3
8 select USB_ARCH_HAS_EHCI 8 select USB_ARCH_HAS_EHCI
9 select USB_EHCI_BIG_ENDIAN_MMIO 9 select USB_EHCI_BIG_ENDIAN_MMIO
10 select MEMORY_HOTPLUG 10 select MEMORY_HOTPLUG
11 select PPC_PCI_CHOICE
11 help 12 help
12 This option enables support for the Sony PS3 game console 13 This option enables support for the Sony PS3 game console
13 and other platforms using the PS3 hypervisor. Enabling this 14 and other platforms using the PS3 hypervisor. Enabling this
diff --git a/arch/powerpc/platforms/ps3/device-init.c b/arch/powerpc/platforms/ps3/device-init.c
index 3866debfa3c4..ffdd8e963fbd 100644
--- a/arch/powerpc/platforms/ps3/device-init.c
+++ b/arch/powerpc/platforms/ps3/device-init.c
@@ -486,6 +486,7 @@ static int __init ps3_register_graphics_devices(void)
486 return -ENOMEM; 486 return -ENOMEM;
487 487
488 p->dev.match_id = PS3_MATCH_ID_GRAPHICS; 488 p->dev.match_id = PS3_MATCH_ID_GRAPHICS;
489 p->dev.match_sub_id = PS3_MATCH_SUB_ID_FB;
489 p->dev.dev_type = PS3_DEVICE_TYPE_IOC0; 490 p->dev.dev_type = PS3_DEVICE_TYPE_IOC0;
490 491
491 result = ps3_system_bus_device_register(&p->dev); 492 result = ps3_system_bus_device_register(&p->dev);
diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c
index d66c3628a112..280ee88cb0b0 100644
--- a/arch/powerpc/platforms/ps3/system-bus.c
+++ b/arch/powerpc/platforms/ps3/system-bus.c
@@ -347,16 +347,23 @@ static int ps3_system_bus_match(struct device *_dev,
347 struct ps3_system_bus_driver *drv = ps3_drv_to_system_bus_drv(_drv); 347 struct ps3_system_bus_driver *drv = ps3_drv_to_system_bus_drv(_drv);
348 struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev); 348 struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev);
349 349
350 result = dev->match_id == drv->match_id; 350 if (!dev->match_sub_id)
351 result = dev->match_id == drv->match_id;
352 else
353 result = dev->match_sub_id == drv->match_sub_id &&
354 dev->match_id == drv->match_id;
351 355
352 if (result) 356 if (result)
353 pr_info("%s:%d: dev=%u(%s), drv=%u(%s): match\n", __func__, 357 pr_info("%s:%d: dev=%u.%u(%s), drv=%u.%u(%s): match\n",
354 __LINE__, dev->match_id, dev->core.bus_id, 358 __func__, __LINE__,
355 drv->match_id, drv->core.name); 359 dev->match_id, dev->match_sub_id, dev->core.bus_id,
360 drv->match_id, drv->match_sub_id, drv->core.name);
356 else 361 else
357 pr_debug("%s:%d: dev=%u(%s), drv=%u(%s): miss\n", __func__, 362 pr_debug("%s:%d: dev=%u.%u(%s), drv=%u.%u(%s): miss\n",
358 __LINE__, dev->match_id, dev->core.bus_id, 363 __func__, __LINE__,
359 drv->match_id, drv->core.name); 364 dev->match_id, dev->match_sub_id, dev->core.bus_id,
365 drv->match_id, drv->match_sub_id, drv->core.name);
366
360 return result; 367 return result;
361} 368}
362 369
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 07fe5b69b9e2..757c0296e0b8 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -7,6 +7,7 @@ config PPC_PSERIES
7 select RTAS_ERROR_LOGGING 7 select RTAS_ERROR_LOGGING
8 select PPC_UDBG_16550 8 select PPC_UDBG_16550
9 select PPC_NATIVE 9 select PPC_NATIVE
10 select PPC_PCI_CHOICE if EMBEDDED
10 default y 11 default y
11 12
12config PPC_SPLPAR 13config PPC_SPLPAR
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index c027f0a70a04..54816d75b578 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -75,9 +75,9 @@
75 */ 75 */
76 76
77/* If a device driver keeps reading an MMIO register in an interrupt 77/* If a device driver keeps reading an MMIO register in an interrupt
78 * handler after a slot isolation event has occurred, we assume it 78 * handler after a slot isolation event, it might be broken.
79 * is broken and panic. This sets the threshold for how many read 79 * This sets the threshold for how many read attempts we allow
80 * attempts we allow before panicking. 80 * before printing an error message.
81 */ 81 */
82#define EEH_MAX_FAILS 2100000 82#define EEH_MAX_FAILS 2100000
83 83
@@ -470,6 +470,7 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
470 unsigned long flags; 470 unsigned long flags;
471 struct pci_dn *pdn; 471 struct pci_dn *pdn;
472 int rc = 0; 472 int rc = 0;
473 const char *location;
473 474
474 total_mmio_ffs++; 475 total_mmio_ffs++;
475 476
@@ -509,18 +510,15 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
509 rc = 1; 510 rc = 1;
510 if (pdn->eeh_mode & EEH_MODE_ISOLATED) { 511 if (pdn->eeh_mode & EEH_MODE_ISOLATED) {
511 pdn->eeh_check_count ++; 512 pdn->eeh_check_count ++;
512 if (pdn->eeh_check_count >= EEH_MAX_FAILS) { 513 if (pdn->eeh_check_count % EEH_MAX_FAILS == 0) {
513 printk (KERN_ERR "EEH: Device driver ignored %d bad reads, panicing\n", 514 location = of_get_property(dn, "ibm,loc-code", NULL);
514 pdn->eeh_check_count); 515 printk (KERN_ERR "EEH: %d reads ignored for recovering device at "
516 "location=%s driver=%s pci addr=%s\n",
517 pdn->eeh_check_count, location,
518 dev->driver->name, pci_name(dev));
519 printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n",
520 dev->driver->name);
515 dump_stack(); 521 dump_stack();
516 msleep(5000);
517
518 /* re-read the slot reset state */
519 if (read_slot_reset_state(pdn, rets) != 0)
520 rets[0] = -1; /* reset state unknown */
521
522 /* If we are here, then we hit an infinite loop. Stop. */
523 panic("EEH: MMIO halt (%d) on device:%s\n", rets[0], pci_name(dev));
524 } 522 }
525 goto dn_unlock; 523 goto dn_unlock;
526 } 524 }
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index 9a12908510fb..5377dd4b849a 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -50,7 +50,8 @@
50 50
51static void tce_build_pSeries(struct iommu_table *tbl, long index, 51static void tce_build_pSeries(struct iommu_table *tbl, long index,
52 long npages, unsigned long uaddr, 52 long npages, unsigned long uaddr,
53 enum dma_data_direction direction) 53 enum dma_data_direction direction,
54 struct dma_attrs *attrs)
54{ 55{
55 u64 proto_tce; 56 u64 proto_tce;
56 u64 *tcep; 57 u64 *tcep;
@@ -95,7 +96,8 @@ static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
95 96
96static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, 97static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
97 long npages, unsigned long uaddr, 98 long npages, unsigned long uaddr,
98 enum dma_data_direction direction) 99 enum dma_data_direction direction,
100 struct dma_attrs *attrs)
99{ 101{
100 u64 rc; 102 u64 rc;
101 u64 proto_tce, tce; 103 u64 proto_tce, tce;
@@ -127,7 +129,8 @@ static DEFINE_PER_CPU(u64 *, tce_page) = NULL;
127 129
128static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, 130static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
129 long npages, unsigned long uaddr, 131 long npages, unsigned long uaddr,
130 enum dma_data_direction direction) 132 enum dma_data_direction direction,
133 struct dma_attrs *attrs)
131{ 134{
132 u64 rc; 135 u64 rc;
133 u64 proto_tce; 136 u64 proto_tce;
@@ -136,7 +139,8 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
136 long l, limit; 139 long l, limit;
137 140
138 if (npages == 1) { 141 if (npages == 1) {
139 tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, direction); 142 tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
143 direction, attrs);
140 return; 144 return;
141 } 145 }
142 146
@@ -150,7 +154,7 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
150 /* If allocation fails, fall back to the loop implementation */ 154 /* If allocation fails, fall back to the loop implementation */
151 if (!tcep) { 155 if (!tcep) {
152 tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, 156 tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
153 direction); 157 direction, attrs);
154 return; 158 return;
155 } 159 }
156 __get_cpu_var(tce_page) = tcep; 160 __get_cpu_var(tce_page) = tcep;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 02:37:55 -0500