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authorGeert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>2009-06-10 00:38:45 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-06-14 23:26:19 -0400
commit5c6fc8db768fb9990ee67ab052896fd46fbe2651 (patch)
treea1e3e051c68ea4101344acffba5ca14363224360 /arch/powerpc/platforms
parentca971ea39fa92add0fa596ad80affd7db781d762 (diff)
powerpc/cell: Extract duplicated IOPTE_* to <asm/iommu.h>
Both arch/powerpc/platforms/cell/iommu.c and arch/powerpc/platforms/ps3/mm.c contain the same Cell IOMMU page table entry definitions. Extract them and move them to <asm/iommu.h>, while adding a CBE_ prefix. This also allows them to be used by drivers. Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/cell/iommu.c37
-rw-r--r--arch/powerpc/platforms/ps3/mm.c7
-rw-r--r--arch/powerpc/platforms/ps3/platform.h10
-rw-r--r--arch/powerpc/platforms/ps3/system-bus.c15
4 files changed, 29 insertions, 40 deletions
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index bed4690de394..5b34fc211f35 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -100,16 +100,6 @@
100#define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */ 100#define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */
101#define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */ 101#define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */
102 102
103/* Page table entries */
104#define IOPTE_PP_W 0x8000000000000000ul /* protection: write */
105#define IOPTE_PP_R 0x4000000000000000ul /* protection: read */
106#define IOPTE_M 0x2000000000000000ul /* coherency required */
107#define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */
108#define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */
109#define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */
110#define IOPTE_H 0x0000000000000800ul /* cache hint */
111#define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */
112
113 103
114/* IOMMU sizing */ 104/* IOMMU sizing */
115#define IO_SEGMENT_SHIFT 28 105#define IO_SEGMENT_SHIFT 28
@@ -193,19 +183,21 @@ static int tce_build_cell(struct iommu_table *tbl, long index, long npages,
193 */ 183 */
194 const unsigned long prot = 0xc48; 184 const unsigned long prot = 0xc48;
195 base_pte = 185 base_pte =
196 ((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R)) 186 ((prot << (52 + 4 * direction)) &
197 | IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask); 187 (CBE_IOPTE_PP_W | CBE_IOPTE_PP_R)) |
188 CBE_IOPTE_M | CBE_IOPTE_SO_RW |
189 (window->ioid & CBE_IOPTE_IOID_Mask);
198#else 190#else
199 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | 191 base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
200 (window->ioid & IOPTE_IOID_Mask); 192 CBE_IOPTE_SO_RW | (window->ioid & CBE_IOPTE_IOID_Mask);
201#endif 193#endif
202 if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))) 194 if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)))
203 base_pte &= ~IOPTE_SO_RW; 195 base_pte &= ~CBE_IOPTE_SO_RW;
204 196
205 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 197 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
206 198
207 for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE) 199 for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE)
208 io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask); 200 io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask);
209 201
210 mb(); 202 mb();
211 203
@@ -231,8 +223,9 @@ static void tce_free_cell(struct iommu_table *tbl, long index, long npages)
231#else 223#else
232 /* spider bridge does PCI reads after freeing - insert a mapping 224 /* spider bridge does PCI reads after freeing - insert a mapping
233 * to a scratch page instead of an invalid entry */ 225 * to a scratch page instead of an invalid entry */
234 pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page) 226 pte = CBE_IOPTE_PP_R | CBE_IOPTE_M | CBE_IOPTE_SO_RW |
235 | (window->ioid & IOPTE_IOID_Mask); 227 __pa(window->iommu->pad_page) |
228 (window->ioid & CBE_IOPTE_IOID_Mask);
236#endif 229#endif
237 230
238 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 231 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
@@ -1001,7 +994,7 @@ static void insert_16M_pte(unsigned long addr, unsigned long *ptab,
1001 pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n", 994 pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n",
1002 addr, ptab, segment, offset); 995 addr, ptab, segment, offset);
1003 996
1004 ptab[offset] = base_pte | (__pa(addr) & IOPTE_RPN_Mask); 997 ptab[offset] = base_pte | (__pa(addr) & CBE_IOPTE_RPN_Mask);
1005} 998}
1006 999
1007static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu, 1000static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
@@ -1016,14 +1009,14 @@ static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
1016 1009
1017 pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase); 1010 pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
1018 1011
1019 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M 1012 base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
1020 | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask); 1013 (cell_iommu_get_ioid(np) & CBE_IOPTE_IOID_Mask);
1021 1014
1022 if (iommu_fixed_is_weak) 1015 if (iommu_fixed_is_weak)
1023 pr_info("IOMMU: Using weak ordering for fixed mapping\n"); 1016 pr_info("IOMMU: Using weak ordering for fixed mapping\n");
1024 else { 1017 else {
1025 pr_info("IOMMU: Using strong ordering for fixed mapping\n"); 1018 pr_info("IOMMU: Using strong ordering for fixed mapping\n");
1026 base_pte |= IOPTE_SO_RW; 1019 base_pte |= CBE_IOPTE_SO_RW;
1027 } 1020 }
1028 1021
1029 for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) { 1022 for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c
index 9a2b6d948610..017b6142caca 100644
--- a/arch/powerpc/platforms/ps3/mm.c
+++ b/arch/powerpc/platforms/ps3/mm.c
@@ -24,6 +24,7 @@
24#include <linux/lmb.h> 24#include <linux/lmb.h>
25 25
26#include <asm/firmware.h> 26#include <asm/firmware.h>
27#include <asm/iommu.h>
27#include <asm/prom.h> 28#include <asm/prom.h>
28#include <asm/udbg.h> 29#include <asm/udbg.h>
29#include <asm/lv1call.h> 30#include <asm/lv1call.h>
@@ -1001,7 +1002,8 @@ static int dma_sb_region_create_linear(struct ps3_dma_region *r)
1001 if (len > r->len) 1002 if (len > r->len)
1002 len = r->len; 1003 len = r->len;
1003 result = dma_sb_map_area(r, virt_addr, len, &tmp, 1004 result = dma_sb_map_area(r, virt_addr, len, &tmp,
1004 IOPTE_PP_W | IOPTE_PP_R | IOPTE_SO_RW | IOPTE_M); 1005 CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_SO_RW |
1006 CBE_IOPTE_M);
1005 BUG_ON(result); 1007 BUG_ON(result);
1006 } 1008 }
1007 1009
@@ -1014,7 +1016,8 @@ static int dma_sb_region_create_linear(struct ps3_dma_region *r)
1014 else 1016 else
1015 len -= map.rm.size - r->offset; 1017 len -= map.rm.size - r->offset;
1016 result = dma_sb_map_area(r, virt_addr, len, &tmp, 1018 result = dma_sb_map_area(r, virt_addr, len, &tmp,
1017 IOPTE_PP_W | IOPTE_PP_R | IOPTE_SO_RW | IOPTE_M); 1019 CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_SO_RW |
1020 CBE_IOPTE_M);
1018 BUG_ON(result); 1021 BUG_ON(result);
1019 } 1022 }
1020 1023
diff --git a/arch/powerpc/platforms/ps3/platform.h b/arch/powerpc/platforms/ps3/platform.h
index 136aa0637d9c..9a196a88eda7 100644
--- a/arch/powerpc/platforms/ps3/platform.h
+++ b/arch/powerpc/platforms/ps3/platform.h
@@ -232,14 +232,4 @@ int ps3_repository_read_spu_resource_id(unsigned int res_index,
232int ps3_repository_read_vuart_av_port(unsigned int *port); 232int ps3_repository_read_vuart_av_port(unsigned int *port);
233int ps3_repository_read_vuart_sysmgr_port(unsigned int *port); 233int ps3_repository_read_vuart_sysmgr_port(unsigned int *port);
234 234
235/* Page table entries */
236#define IOPTE_PP_W 0x8000000000000000ul /* protection: write */
237#define IOPTE_PP_R 0x4000000000000000ul /* protection: read */
238#define IOPTE_M 0x2000000000000000ul /* coherency required */
239#define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */
240#define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */
241#define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */
242#define IOPTE_H 0x0000000000000800ul /* cache hint */
243#define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */
244
245#endif 235#endif
diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c
index 9a73d0238639..9fead0faf38b 100644
--- a/arch/powerpc/platforms/ps3/system-bus.c
+++ b/arch/powerpc/platforms/ps3/system-bus.c
@@ -27,6 +27,7 @@
27#include <asm/udbg.h> 27#include <asm/udbg.h>
28#include <asm/lv1call.h> 28#include <asm/lv1call.h>
29#include <asm/firmware.h> 29#include <asm/firmware.h>
30#include <asm/iommu.h>
30 31
31#include "platform.h" 32#include "platform.h"
32 33
@@ -531,7 +532,8 @@ static void * ps3_alloc_coherent(struct device *_dev, size_t size,
531 } 532 }
532 533
533 result = ps3_dma_map(dev->d_region, virt_addr, size, dma_handle, 534 result = ps3_dma_map(dev->d_region, virt_addr, size, dma_handle,
534 IOPTE_PP_W | IOPTE_PP_R | IOPTE_SO_RW | IOPTE_M); 535 CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
536 CBE_IOPTE_SO_RW | CBE_IOPTE_M);
535 537
536 if (result) { 538 if (result) {
537 pr_debug("%s:%d: ps3_dma_map failed (%d)\n", 539 pr_debug("%s:%d: ps3_dma_map failed (%d)\n",
@@ -575,7 +577,8 @@ static dma_addr_t ps3_sb_map_page(struct device *_dev, struct page *page,
575 577
576 result = ps3_dma_map(dev->d_region, (unsigned long)ptr, size, 578 result = ps3_dma_map(dev->d_region, (unsigned long)ptr, size,
577 &bus_addr, 579 &bus_addr,
578 IOPTE_PP_R | IOPTE_PP_W | IOPTE_SO_RW | IOPTE_M); 580 CBE_IOPTE_PP_R | CBE_IOPTE_PP_W |
581 CBE_IOPTE_SO_RW | CBE_IOPTE_M);
579 582
580 if (result) { 583 if (result) {
581 pr_debug("%s:%d: ps3_dma_map failed (%d)\n", 584 pr_debug("%s:%d: ps3_dma_map failed (%d)\n",
@@ -596,16 +599,16 @@ static dma_addr_t ps3_ioc0_map_page(struct device *_dev, struct page *page,
596 u64 iopte_flag; 599 u64 iopte_flag;
597 void *ptr = page_address(page) + offset; 600 void *ptr = page_address(page) + offset;
598 601
599 iopte_flag = IOPTE_M; 602 iopte_flag = CBE_IOPTE_M;
600 switch (direction) { 603 switch (direction) {
601 case DMA_BIDIRECTIONAL: 604 case DMA_BIDIRECTIONAL:
602 iopte_flag |= IOPTE_PP_R | IOPTE_PP_W | IOPTE_SO_RW; 605 iopte_flag |= CBE_IOPTE_PP_R | CBE_IOPTE_PP_W | CBE_IOPTE_SO_RW;
603 break; 606 break;
604 case DMA_TO_DEVICE: 607 case DMA_TO_DEVICE:
605 iopte_flag |= IOPTE_PP_R | IOPTE_SO_R; 608 iopte_flag |= CBE_IOPTE_PP_R | CBE_IOPTE_SO_R;
606 break; 609 break;
607 case DMA_FROM_DEVICE: 610 case DMA_FROM_DEVICE:
608 iopte_flag |= IOPTE_PP_W | IOPTE_SO_RW; 611 iopte_flag |= CBE_IOPTE_PP_W | CBE_IOPTE_SO_RW;
609 break; 612 break;
610 default: 613 default:
611 /* not happned */ 614 /* not happned */