diff options
author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2008-12-18 14:13:32 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2008-12-20 22:21:16 -0500 |
commit | 7c03d653cd257793dc40520c94e229b5fd0578e7 (patch) | |
tree | c2beffddec486c47f8ec6df5c3b592c143380559 /arch/powerpc/platforms | |
parent | 2ca8cf738907180e7fbda90f25f32b86feda609f (diff) |
powerpc/mm: Introduce MMU features
We're soon running out of CPU features and I need to add some new
ones for various MMU related bits, so this patch separates the MMU
features from the CPU features. I moved over the 32-bit MMU related
ones, added base features for MMU type families, but didn't move
over any 64-bit only feature yet.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r-- | arch/powerpc/platforms/powermac/sleep.S | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/powerpc/platforms/powermac/sleep.S b/arch/powerpc/platforms/powermac/sleep.S index adee28da353f..1c2802fabd57 100644 --- a/arch/powerpc/platforms/powermac/sleep.S +++ b/arch/powerpc/platforms/powermac/sleep.S | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <asm/cache.h> | 17 | #include <asm/cache.h> |
18 | #include <asm/thread_info.h> | 18 | #include <asm/thread_info.h> |
19 | #include <asm/asm-offsets.h> | 19 | #include <asm/asm-offsets.h> |
20 | #include <asm/mmu.h> | ||
20 | 21 | ||
21 | #define MAGIC 0x4c617273 /* 'Lars' */ | 22 | #define MAGIC 0x4c617273 /* 'Lars' */ |
22 | 23 | ||
@@ -323,7 +324,7 @@ grackle_wake_up: | |||
323 | lwz r4,SL_IBAT3+4(r1) | 324 | lwz r4,SL_IBAT3+4(r1) |
324 | mtibatl 3,r4 | 325 | mtibatl 3,r4 |
325 | 326 | ||
326 | BEGIN_FTR_SECTION | 327 | BEGIN_MMU_FTR_SECTION |
327 | li r4,0 | 328 | li r4,0 |
328 | mtspr SPRN_DBAT4U,r4 | 329 | mtspr SPRN_DBAT4U,r4 |
329 | mtspr SPRN_DBAT4L,r4 | 330 | mtspr SPRN_DBAT4L,r4 |
@@ -341,7 +342,7 @@ BEGIN_FTR_SECTION | |||
341 | mtspr SPRN_IBAT6L,r4 | 342 | mtspr SPRN_IBAT6L,r4 |
342 | mtspr SPRN_IBAT7U,r4 | 343 | mtspr SPRN_IBAT7U,r4 |
343 | mtspr SPRN_IBAT7L,r4 | 344 | mtspr SPRN_IBAT7L,r4 |
344 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) | 345 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
345 | 346 | ||
346 | /* Flush all TLBs */ | 347 | /* Flush all TLBs */ |
347 | lis r4,0x1000 | 348 | lis r4,0x1000 |