Merge commit 'kumar/kumar-next'

11 files changed, 364 insertions, 11 deletions

diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index c62f893ede19..326852c78b8f 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -3,6 +3,8 @@ config PPC_MPC512x
         select FSL_SOC
         select IPIC
         select PPC_CLOCK
+        select PPC_PCI_CHOICE
+        select FSL_PCI if PCI
 
 config PPC_MPC5121
         bool
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads.c b/arch/powerpc/platforms/512x/mpc5121_ads.c
index 5ebf6939a697..441abc488851 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads.c
@@ -22,16 +22,26 @@
 #include <asm/prom.h>
 #include <asm/time.h>
 
+#include <sysdev/fsl_pci.h>
+
 #include "mpc512x.h"
 #include "mpc5121_ads.h"
 
 static void __init mpc5121_ads_setup_arch(void)
 {
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
         printk(KERN_INFO "MPC5121 ADS board from Freescale Semiconductor\n");
         /*
          * cpld regs are needed early
          */
         mpc5121_ads_cpld_map();
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,mpc5121-pci")
+                mpc83xx_add_bridge(np);
+#endif
 }
 
 static void __init mpc5121_ads_init_IRQ(void)
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 6159c5d4e5f1..83c664afc897 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -19,7 +19,6 @@ config MPC831x_RDB
 config MPC832x_MDS
         bool "Freescale MPC832x MDS"
         select DEFAULT_UIMAGE
-        select QUICC_ENGINE
         select PPC_MPC832x
         help
           This option enables support for the MPC832x MDS evaluation board.
@@ -27,7 +26,6 @@ config MPC832x_MDS
 config MPC832x_RDB
         bool "Freescale MPC832x RDB"
         select DEFAULT_UIMAGE
-        select QUICC_ENGINE
         select PPC_MPC832x
         help
           This option enables support for the MPC8323 RDB board.
@@ -57,15 +55,12 @@ config MPC834x_ITX
 config MPC836x_MDS
         bool "Freescale MPC836x MDS"
         select DEFAULT_UIMAGE
-        select QUICC_ENGINE
         help
           This option enables support for the MPC836x MDS Processor Board.
 
 config MPC836x_RDK
         bool "Freescale/Logic MPC836x RDK"
         select DEFAULT_UIMAGE
-        select QUICC_ENGINE
-        select QE_GPIO
         select FSL_GTM
         select FSL_LBC
         help
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index be62de23bead..8bb13c807142 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -85,8 +85,14 @@ static void __init mpc837x_mds_setup_arch(void)
                 ppc_md.progress("mpc837x_mds_setup_arch()", 0);
 
 #ifdef CONFIG_PCI
-        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
+        for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") {
+                if (!of_device_is_available(np)) {
+                        pr_warning("%s: disabled by the firmware.\n",
+                                   np->full_name);
+                        continue;
+                }
                 mpc83xx_add_bridge(np);
+        }
 #endif
         mpc837xmds_usb_cfg();
 }
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 291675b0097a..b79dc710ed34 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -33,7 +33,6 @@ config MPC85xx_CDS
 config MPC85xx_MDS
         bool "Freescale MPC85xx MDS"
         select DEFAULT_UIMAGE
-        select QUICC_ENGINE
         select PHYLIB
         help
           This option enables support for the MPC85xx MDS board
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index cb9fc8f4360b..4a56ff619afd 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -7,4 +7,4 @@ obj-$(CONFIG_SMP)		+= mpc86xx_smp.o
 obj-$(CONFIG_MPC8641_HPCN)      += mpc86xx_hpcn.o
 obj-$(CONFIG_SBC8641D)          += sbc8641d.o
 obj-$(CONFIG_MPC8610_HPCD)      += mpc8610_hpcd.o
-obj-$(CONFIG_GEF_SBC610)        += gef_sbc610.o
+obj-$(CONFIG_GEF_SBC610)        += gef_sbc610.o gef_pic.o
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c
new file mode 100644
index 000000000000..50d0a2b63809
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/gef_pic.c
@@ -0,0 +1,258 @@
+/*
+ * Interrupt handling for GE Fanuc's FPGA based PIC
+ *
+ * Author: Martyn Welch <martyn.welch@gefanuc.com>
+ *
+ * 2008 (c) GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/irq.h>
+
+#include "gef_pic.h"
+
+#define DEBUG
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt...) do { printk(KERN_DEBUG "gef_pic: " fmt); } while (0)
+#else
+#define DBG(fmt...) do { } while (0)
+#endif
+
+#define GEF_PIC_NUM_IRQS        32
+
+/* Interrupt Controller Interface Registers */
+#define GEF_PIC_INTR_STATUS     0x0000
+
+#define GEF_PIC_INTR_MASK(cpu)  (0x0010 + (0x4 * cpu))
+#define GEF_PIC_CPU0_INTR_MASK  GEF_PIC_INTR_MASK(0)
+#define GEF_PIC_CPU1_INTR_MASK  GEF_PIC_INTR_MASK(1)
+
+#define GEF_PIC_MCP_MASK(cpu)   (0x0018 + (0x4 * cpu))
+#define GEF_PIC_CPU0_MCP_MASK   GEF_PIC_MCP_MASK(0)
+#define GEF_PIC_CPU1_MCP_MASK   GEF_PIC_MCP_MASK(1)
+
+#define gef_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
+
+
+static DEFINE_SPINLOCK(gef_pic_lock);
+
+static void __iomem *gef_pic_irq_reg_base;
+static struct irq_host *gef_pic_irq_host;
+static int gef_pic_cascade_irq;
+
+/*
+ * Interrupt Controller Handling
+ *
+ * The interrupt controller handles interrupts for most on board interrupts,
+ * apart from PCI interrupts. For example on SBC610:
+ *
+ * 17:31 RO Reserved
+ * 16    RO PCI Express Doorbell 3 Status
+ * 15    RO PCI Express Doorbell 2 Status
+ * 14    RO PCI Express Doorbell 1 Status
+ * 13    RO PCI Express Doorbell 0 Status
+ * 12    RO Real Time Clock Interrupt Status
+ * 11    RO Temperature Interrupt Status
+ * 10    RO Temperature Critical Interrupt Status
+ * 9     RO Ethernet PHY1 Interrupt Status
+ * 8     RO Ethernet PHY3 Interrupt Status
+ * 7     RO PEX8548 Interrupt Status
+ * 6     RO Reserved
+ * 5     RO Watchdog 0 Interrupt Status
+ * 4     RO Watchdog 1 Interrupt Status
+ * 3     RO AXIS Message FIFO A Interrupt Status
+ * 2     RO AXIS Message FIFO B Interrupt Status
+ * 1     RO AXIS Message FIFO C Interrupt Status
+ * 0     RO AXIS Message FIFO D Interrupt Status
+ *
+ * Interrupts can be forwarded to one of two output lines. Nothing
+ * clever is done, so if the masks are incorrectly set, a single input
+ * interrupt could generate interrupts on both output lines!
+ *
+ * The dual lines are there to allow the chained interrupts to be easily
+ * passed into two different cores. We currently do not use this functionality
+ * in this driver.
+ *
+ * Controller can also be configured to generate Machine checks (MCP), again on
+ * two lines, to be attached to two different cores. It is suggested that these
+ * should be masked out.
+ */
+
+void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned int cascade_irq;
+
+        /*
+         * See if we actually have an interrupt, call generic handling code if
+         * we do.
+         */
+        cascade_irq = gef_pic_get_irq();
+
+        if (cascade_irq != NO_IRQ)
+                generic_handle_irq(cascade_irq);
+
+        desc->chip->eoi(irq);
+
+}
+
+static void gef_pic_mask(unsigned int virq)
+{
+        unsigned long flags;
+        unsigned int hwirq;
+        u32 mask;
+
+        hwirq = gef_irq_to_hw(virq);
+
+        spin_lock_irqsave(&gef_pic_lock, flags);
+        mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
+        mask &= ~(1 << hwirq);
+        out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
+        spin_unlock_irqrestore(&gef_pic_lock, flags);
+}
+
+static void gef_pic_mask_ack(unsigned int virq)
+{
+        /* Don't think we actually have to do anything to ack an interrupt,
+         * we just need to clear down the devices interrupt and it will go away
+         */
+        gef_pic_mask(virq);
+}
+
+static void gef_pic_unmask(unsigned int virq)
+{
+        unsigned long flags;
+        unsigned int hwirq;
+        u32 mask;
+
+        hwirq = gef_irq_to_hw(virq);
+
+        spin_lock_irqsave(&gef_pic_lock, flags);
+        mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
+        mask |= (1 << hwirq);
+        out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
+        spin_unlock_irqrestore(&gef_pic_lock, flags);
+}
+
+static struct irq_chip gef_pic_chip = {
+        .typename       = "gefp",
+        .mask           = gef_pic_mask,
+        .mask_ack       = gef_pic_mask_ack,
+        .unmask         = gef_pic_unmask,
+};
+
+
+/* When an interrupt is being configured, this call allows some flexibilty
+ * in deciding which irq_chip structure is used
+ */
+static int gef_pic_host_map(struct irq_host *h, unsigned int virq,
+                          irq_hw_number_t hwirq)
+{
+        /* All interrupts are LEVEL sensitive */
+        get_irq_desc(virq)->status |= IRQ_LEVEL;
+        set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
+
+        return 0;
+}
+
+static int gef_pic_host_xlate(struct irq_host *h, struct device_node *ct,
+                            u32 *intspec, unsigned int intsize,
+                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
+{
+
+        *out_hwirq = intspec[0];
+        if (intsize > 1)
+                *out_flags = intspec[1];
+        else
+                *out_flags = IRQ_TYPE_LEVEL_HIGH;
+
+        return 0;
+}
+
+static struct irq_host_ops gef_pic_host_ops = {
+        .map    = gef_pic_host_map,
+        .xlate  = gef_pic_host_xlate,
+};
+
+
+/*
+ * Initialisation of PIC, this should be called in BSP
+ */
+void __init gef_pic_init(struct device_node *np)
+{
+        unsigned long flags;
+
+        /* Map the devices registers into memory */
+        gef_pic_irq_reg_base = of_iomap(np, 0);
+
+        spin_lock_irqsave(&gef_pic_lock, flags);
+
+        /* Initialise everything as masked. */
+        out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0);
+        out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_INTR_MASK, 0);
+
+        out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0);
+        out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0);
+
+        spin_unlock_irqrestore(&gef_pic_lock, flags);
+
+        /* Map controller */
+        gef_pic_cascade_irq = irq_of_parse_and_map(np, 0);
+        if (gef_pic_cascade_irq == NO_IRQ) {
+                printk(KERN_ERR "SBC610: failed to map cascade interrupt");
+                return;
+        }
+
+        /* Setup an irq_host structure */
+        gef_pic_irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
+                                          GEF_PIC_NUM_IRQS,
+                                          &gef_pic_host_ops, NO_IRQ);
+        if (gef_pic_irq_host == NULL)
+                return;
+
+        /* Chain with parent controller */
+        set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
+}
+
+/*
+ * This is called when we receive an interrupt with apparently comes from this
+ * chip - check, returning the highest interrupt generated or return NO_IRQ
+ */
+unsigned int gef_pic_get_irq(void)
+{
+        u32 cause, mask, active;
+        unsigned int virq = NO_IRQ;
+        int hwirq;
+
+        cause = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_STATUS);
+
+        mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
+
+        active = cause & mask;
+
+        if (active) {
+                for (hwirq = GEF_PIC_NUM_IRQS - 1; hwirq > -1; hwirq--) {
+                        if (active & (0x1 << hwirq))
+                                break;
+                }
+                virq = irq_linear_revmap(gef_pic_irq_host,
+                        (irq_hw_number_t)hwirq);
+        }
+
+        return virq;
+}
+
diff --git a/arch/powerpc/platforms/86xx/gef_pic.h b/arch/powerpc/platforms/86xx/gef_pic.h
new file mode 100644
index 000000000000..6149916da3f4
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/gef_pic.h
@@ -0,0 +1,11 @@
+#ifndef __GEF_PIC_H__
+#define __GEF_PIC_H__
+
+#include <linux/init.h>
+
+void gef_pic_cascade(unsigned int, struct irq_desc *);
+unsigned int gef_pic_get_irq(void);
+void gef_pic_init(struct device_node *);
+
+#endif /* __GEF_PIC_H__ */
+
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index ee215002b1cf..821c45fac18b 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -39,6 +39,7 @@
 #include <sysdev/fsl_soc.h>
 
 #include "mpc86xx.h"
+#include "gef_pic.h"
 
 #undef DEBUG
 
@@ -48,8 +49,31 @@
 #define DBG (fmt...) do { } while (0)
 #endif
 
+void __iomem *sbc610_regs;
+
+static void __init gef_sbc610_init_irq(void)
+{
+        struct device_node *cascade_node = NULL;
+
+        mpc86xx_init_irq();
+
+        /*
+         * There is a simple interrupt handler in the main FPGA, this needs
+         * to be cascaded into the MPIC
+         */
+        cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
+        if (!cascade_node) {
+                printk(KERN_WARNING "SBC610: No FPGA PIC\n");
+                return;
+        }
+
+        gef_pic_init(cascade_node);
+        of_node_put(cascade_node);
+}
+
 static void __init gef_sbc610_setup_arch(void)
 {
+        struct device_node *regs;
 #ifdef CONFIG_PCI
         struct device_node *np;
 
@@ -63,8 +87,43 @@ static void __init gef_sbc610_setup_arch(void)
 #ifdef CONFIG_SMP
         mpc86xx_smp_init();
 #endif
+
+        /* Remap basic board registers */
+        regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
+        if (regs) {
+                sbc610_regs = of_iomap(regs, 0);
+                if (sbc610_regs == NULL)
+                        printk(KERN_WARNING "Unable to map board registers\n");
+                of_node_put(regs);
+        }
+}
+
+/* Return the PCB revision */
+static unsigned int gef_sbc610_get_pcb_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread32(sbc610_regs);
+        return (reg >> 8) & 0xff;
+}
+
+/* Return the board (software) revision */
+static unsigned int gef_sbc610_get_board_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread32(sbc610_regs);
+        return (reg >> 16) & 0xff;
 }
 
+/* Return the FPGA revision */
+static unsigned int gef_sbc610_get_fpga_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread32(sbc610_regs);
+        return (reg >> 24) & 0xf;
+}
 
 static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 {
@@ -73,6 +132,10 @@ static void gef_sbc610_show_cpuinfo(struct seq_file *m)
 
         seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
 
+        seq_printf(m, "Revision\t: %u%c\n", gef_sbc610_get_pcb_rev(),
+                ('A' + gef_sbc610_get_board_rev() - 1));
+        seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc610_get_fpga_rev());
+
         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 }
@@ -145,7 +208,7 @@ define_machine(gef_sbc610) {
         .name                   = "GE Fanuc SBC610",
         .probe                  = gef_sbc610_probe,
         .setup_arch             = gef_sbc610_setup_arch,
-        .init_IRQ               = mpc86xx_init_irq,
+        .init_IRQ               = gef_sbc610_init_irq,
         .show_cpuinfo           = gef_sbc610_show_cpuinfo,
         .get_irq                = mpic_get_irq,
         .restart                = fsl_rstcr_restart,
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 5eedb710896e..e8d54ac5292c 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -238,7 +238,6 @@ static void __init mpc86xx_hpcd_setup_arch(void)
         }
 #endif
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
-        preallocate_diu_videomemory();
         diu_ops.get_pixel_format        = mpc8610hpcd_get_pixel_format;
         diu_ops.set_gamma_table         = mpc8610hpcd_set_gamma_table;
         diu_ops.set_monitor_port        = mpc8610hpcd_set_monitor_port;
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 9578c45b04fe..47e956c871fe 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -239,7 +239,8 @@ config TAU_AVERAGE
           If in doubt, say N here.
 
 config QUICC_ENGINE
-        bool
+        bool "Freescale QUICC Engine (QE) Support"
+        depends on FSL_SOC
         select PPC_LIB_RHEAP
         select CRC32
         help
@@ -248,6 +249,15 @@ config QUICC_ENGINE
           Selecting this option means that you wish to build a kernel
           for a machine with a QE coprocessor.
 
+config QE_GPIO
+        bool "QE GPIO support"
+        depends on QUICC_ENGINE
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        help
+          Say Y here if you're going to use hardware that connects to the
+          QE GPIOs.
+
 config CPM2
         bool "Enable support for the CPM2 (Communications Processor Module)"
         depends on MPC85xx || 8260