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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-02-05 08:50:04 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-02-13 23:01:38 -0500
commit454c0bfd0c6469276dec766e5b41efcf0ccf2619 (patch)
tree99b362fb2add3a0e5c9da2b1ed3e2624214bf8ef /arch/powerpc/platforms/wsp
parent3ec1e88b33a3bdd852ce8e014052acec7a9da8b5 (diff)
powerpc/wsp: Permanently enable PCI class code workaround
It appears that on the Chroma card, the class code of the root complex is still wrong even on DD2 or later chips. This could be a firmware issue, but that breaks resource allocation so let's unconditionally fix it up. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/platforms/wsp')
-rw-r--r--arch/powerpc/platforms/wsp/wsp_pci.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/platforms/wsp/wsp_pci.c b/arch/powerpc/platforms/wsp/wsp_pci.c
index e0262cd0e2d3..d24b3acf858e 100644
--- a/arch/powerpc/platforms/wsp/wsp_pci.c
+++ b/arch/powerpc/platforms/wsp/wsp_pci.c
@@ -468,15 +468,15 @@ static void __init wsp_pcie_configure_hw(struct pci_controller *hose)
468#define DUMP_REG(x) \ 468#define DUMP_REG(x) \
469 pr_debug("%-30s : 0x%016llx\n", #x, in_be64(hose->cfg_data + x)) 469 pr_debug("%-30s : 0x%016llx\n", #x, in_be64(hose->cfg_data + x))
470 470
471#ifdef CONFIG_WSP_DD1_WORKAROUND_BAD_PCIE_CLASS 471 /*
472 /* WSP DD1 has a bogus class code by default in the PCI-E 472 * Some WSP variants has a bogus class code by default in the PCI-E
473 * root complex's built-in P2P bridge */ 473 * root complex's built-in P2P bridge
474 */
474 val = in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1); 475 val = in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1);
475 pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", val); 476 pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", val);
476 out_be64(hose->cfg_data + PCIE_REG_SYS_CFG1, 477 out_be64(hose->cfg_data + PCIE_REG_SYS_CFG1,
477 (val & ~PCIE_REG_SYS_CFG1_CLASS_CODE) | (PCI_CLASS_BRIDGE_PCI << 8)); 478 (val & ~PCIE_REG_SYS_CFG1_CLASS_CODE) | (PCI_CLASS_BRIDGE_PCI << 8));
478 pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1)); 479 pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1));
479#endif /* CONFIG_WSP_DD1_WORKAROUND_BAD_PCIE_CLASS */
480 480
481#ifdef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS 481#ifdef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS
482 /* XXX Disable TCE caching, it doesn't work on DD1 */ 482 /* XXX Disable TCE caching, it doesn't work on DD1 */