diff options
| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2006-03-23 01:38:10 -0500 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-03-26 22:48:08 -0500 |
| commit | af308377e204e25f1f58627d05fe0f483703b514 (patch) | |
| tree | bed18644cbf621ecb5447e626e6a0957ab363a46 /arch/powerpc/platforms/powermac/nvram.c | |
| parent | 7c92943c7b6c42fa631ac2b67aeb507e727cd75b (diff) | |
[PATCH] powerpc: fix various sparse warnings
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/powermac/nvram.c')
| -rw-r--r-- | arch/powerpc/platforms/powermac/nvram.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/powerpc/platforms/powermac/nvram.c b/arch/powerpc/platforms/powermac/nvram.c index 5fd28995c74c..3aa3477b86f7 100644 --- a/arch/powerpc/platforms/powermac/nvram.c +++ b/arch/powerpc/platforms/powermac/nvram.c | |||
| @@ -74,7 +74,7 @@ struct core99_header { | |||
| 74 | * Read and write the non-volatile RAM on PowerMacs and CHRP machines. | 74 | * Read and write the non-volatile RAM on PowerMacs and CHRP machines. |
| 75 | */ | 75 | */ |
| 76 | static int nvram_naddrs; | 76 | static int nvram_naddrs; |
| 77 | static volatile unsigned char *nvram_data; | 77 | static volatile unsigned char __iomem *nvram_data; |
| 78 | static int is_core_99; | 78 | static int is_core_99; |
| 79 | static int core99_bank = 0; | 79 | static int core99_bank = 0; |
| 80 | static int nvram_partitions[3]; | 80 | static int nvram_partitions[3]; |
| @@ -148,7 +148,7 @@ static ssize_t core99_nvram_size(void) | |||
| 148 | } | 148 | } |
| 149 | 149 | ||
| 150 | #ifdef CONFIG_PPC32 | 150 | #ifdef CONFIG_PPC32 |
| 151 | static volatile unsigned char *nvram_addr; | 151 | static volatile unsigned char __iomem *nvram_addr; |
| 152 | static int nvram_mult; | 152 | static int nvram_mult; |
| 153 | 153 | ||
| 154 | static unsigned char direct_nvram_read_byte(int addr) | 154 | static unsigned char direct_nvram_read_byte(int addr) |
| @@ -285,7 +285,7 @@ static int sm_erase_bank(int bank) | |||
| 285 | int stat, i; | 285 | int stat, i; |
| 286 | unsigned long timeout; | 286 | unsigned long timeout; |
| 287 | 287 | ||
| 288 | u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE; | 288 | u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; |
| 289 | 289 | ||
| 290 | DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank); | 290 | DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank); |
| 291 | 291 | ||
| @@ -317,7 +317,7 @@ static int sm_write_bank(int bank, u8* datas) | |||
| 317 | int i, stat = 0; | 317 | int i, stat = 0; |
| 318 | unsigned long timeout; | 318 | unsigned long timeout; |
| 319 | 319 | ||
| 320 | u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE; | 320 | u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; |
| 321 | 321 | ||
| 322 | DBG("nvram: Sharp/Micron Writing bank %d...\n", bank); | 322 | DBG("nvram: Sharp/Micron Writing bank %d...\n", bank); |
| 323 | 323 | ||
| @@ -352,7 +352,7 @@ static int amd_erase_bank(int bank) | |||
| 352 | int i, stat = 0; | 352 | int i, stat = 0; |
| 353 | unsigned long timeout; | 353 | unsigned long timeout; |
| 354 | 354 | ||
| 355 | u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE; | 355 | u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; |
| 356 | 356 | ||
| 357 | DBG("nvram: AMD Erasing bank %d...\n", bank); | 357 | DBG("nvram: AMD Erasing bank %d...\n", bank); |
| 358 | 358 | ||
| @@ -399,7 +399,7 @@ static int amd_write_bank(int bank, u8* datas) | |||
| 399 | int i, stat = 0; | 399 | int i, stat = 0; |
| 400 | unsigned long timeout; | 400 | unsigned long timeout; |
| 401 | 401 | ||
| 402 | u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE; | 402 | u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE; |
| 403 | 403 | ||
| 404 | DBG("nvram: AMD Writing bank %d...\n", bank); | 404 | DBG("nvram: AMD Writing bank %d...\n", bank); |
| 405 | 405 | ||