Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (408 commits)
  [POWERPC] Add memchr() to the bootwrapper
  [POWERPC] Implement logging of unhandled signals
  [POWERPC] Add legacy serial support for OPB with flattened device tree
  [POWERPC] Use 1TB segments
  [POWERPC] XilinxFB: Allow fixed framebuffer base address
  [POWERPC] XilinxFB: Add support for custom screen resolution
  [POWERPC] XilinxFB: Use pdata to pass around framebuffer parameters
  [POWERPC] PCI: Add 64-bit physical address support to setup_indirect_pci
  [POWERPC] 4xx: Kilauea defconfig file
  [POWERPC] 4xx: Kilauea DTS
  [POWERPC] 4xx: Add AMCC Kilauea eval board support to platforms/40x
  [POWERPC] 4xx: Add AMCC 405EX support to cputable.c
  [POWERPC] Adjust TASK_SIZE on ppc32 systems to 3GB that are capable
  [POWERPC] Use PAGE_OFFSET to tell if an address is user/kernel in SW TLB handlers
  [POWERPC] 85xx: Enable FP emulation in MPC8560 ADS defconfig
  [POWERPC] 85xx: Killed <asm/mpc85xx.h>
  [POWERPC] 85xx: Add cpm nodes for 8541/8555 CDS
  [POWERPC] 85xx: Convert mpc8560ads to the new CPM binding.
  [POWERPC] mpc8272ads: Remove muram from the CPM reg property.
  [POWERPC] Make clockevents work on PPC601 processors
  ...

Fixed up conflict in Documentation/powerpc/booting-without-of.txt manually.

7 files changed, 203 insertions, 26 deletions

diff --git a/arch/powerpc/platforms/pasemi/Kconfig b/arch/powerpc/platforms/pasemi/Kconfig
index e95261ef6f98..735e1536cbfc 100644
--- a/arch/powerpc/platforms/pasemi/Kconfig
+++ b/arch/powerpc/platforms/pasemi/Kconfig
@@ -5,6 +5,7 @@ config PPC_PASEMI
         select MPIC
         select PPC_UDBG_16550
         select PPC_NATIVE
+        select MPIC_BROKEN_REGREAD
         help
           This option enables support for PA Semi's PWRficient line
           of SoC processors, including PA6T-1682M
diff --git a/arch/powerpc/platforms/pasemi/gpio_mdio.c b/arch/powerpc/platforms/pasemi/gpio_mdio.c
index c91a33593bb8..dae9f658122e 100644
--- a/arch/powerpc/platforms/pasemi/gpio_mdio.c
+++ b/arch/powerpc/platforms/pasemi/gpio_mdio.c
@@ -320,10 +320,12 @@ static struct of_device_id gpio_mdio_match[] =
 
 static struct of_platform_driver gpio_mdio_driver =
 {
-        .name           = "gpio-mdio-bitbang",
         .match_table    = gpio_mdio_match,
         .probe          = gpio_mdio_probe,
         .remove         = gpio_mdio_remove,
+        .driver         = {
+                .name   = "gpio-mdio-bitbang",
+        },
 };
 
 int gpio_mdio_init(void)
diff --git a/arch/powerpc/platforms/pasemi/idle.c b/arch/powerpc/platforms/pasemi/idle.c
index 3c962d5757be..d8e1fcc78513 100644
--- a/arch/powerpc/platforms/pasemi/idle.c
+++ b/arch/powerpc/platforms/pasemi/idle.c
@@ -72,8 +72,11 @@ static int pasemi_system_reset_exception(struct pt_regs *regs)
         return 1;
 }
 
-void __init pasemi_idle_init(void)
+static int __init pasemi_idle_init(void)
 {
+        if (!machine_is(pasemi))
+                return -ENODEV;
+
 #ifndef CONFIG_PPC_PASEMI_CPUFREQ
         printk(KERN_WARNING "No cpufreq driver, powersavings modes disabled\n");
         current_mode = 0;
@@ -82,7 +85,10 @@ void __init pasemi_idle_init(void)
         ppc_md.system_reset_exception = pasemi_system_reset_exception;
         ppc_md.power_save = modes[current_mode].entry;
         printk(KERN_INFO "Using PA6T idle loop (%s)\n", modes[current_mode].name);
+
+        return 0;
 }
+late_initcall(pasemi_idle_init);
 
 static int __init idle_param(char *p)
 {
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index a1111b5c6cb4..9916a0f3e431 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -192,7 +192,7 @@ static void pci_dma_dev_setup_pasemi(struct pci_dev *dev)
 static void pci_dma_bus_setup_null(struct pci_bus *b) { }
 static void pci_dma_dev_setup_null(struct pci_dev *d) { }
 
-int iob_init(struct device_node *dn)
+int __init iob_init(struct device_node *dn)
 {
         unsigned long tmp;
         u32 regword;
@@ -238,7 +238,7 @@ int iob_init(struct device_node *dn)
 
 
 /* These are called very early. */
-void iommu_init_early_pasemi(void)
+void __init iommu_init_early_pasemi(void)
 {
         int iommu_off;
 
diff --git a/arch/powerpc/platforms/pasemi/pasemi.h b/arch/powerpc/platforms/pasemi/pasemi.h
index be8495497611..516acabb4e96 100644
--- a/arch/powerpc/platforms/pasemi/pasemi.h
+++ b/arch/powerpc/platforms/pasemi/pasemi.h
@@ -6,9 +6,9 @@ extern void pas_pci_init(void);
 extern void __devinit pas_pci_irq_fixup(struct pci_dev *dev);
 extern void __devinit pas_pci_dma_dev_setup(struct pci_dev *dev);
 
-extern void __init alloc_iobmap_l2(void);
+extern void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset);
 
-extern void __init pasemi_idle_init(void);
+extern void __init alloc_iobmap_l2(void);
 
 /* Power savings modes, implemented in asm */
 extern void idle_spin(void);
diff --git a/arch/powerpc/platforms/pasemi/pci.c b/arch/powerpc/platforms/pasemi/pci.c
index ab1f5f62bcd8..b6a0ec45c695 100644
--- a/arch/powerpc/platforms/pasemi/pci.c
+++ b/arch/powerpc/platforms/pasemi/pci.c
@@ -51,6 +51,61 @@ static void volatile __iomem *pa_pxp_cfg_addr(struct pci_controller *hose,
         return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset);
 }
 
+static inline int is_root_port(int busno, int devfn)
+{
+        return ((busno == 0) && (PCI_FUNC(devfn) < 4) &&
+                 ((PCI_SLOT(devfn) == 16) || (PCI_SLOT(devfn) == 17)));
+}
+
+static inline int is_5945_reg(int reg)
+{
+        return (((reg >= 0x18) && (reg < 0x34)) ||
+                ((reg >= 0x158) && (reg < 0x178)));
+}
+
+static int workaround_5945(struct pci_bus *bus, unsigned int devfn,
+                           int offset, int len, u32 *val)
+{
+        struct pci_controller *hose;
+        void volatile __iomem *addr, *dummy;
+        int byte;
+        u32 tmp;
+
+        if (!is_root_port(bus->number, devfn) || !is_5945_reg(offset))
+                return 0;
+
+        hose = pci_bus_to_host(bus);
+
+        addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset & ~0x3);
+        byte = offset & 0x3;
+
+        /* Workaround bug 5945: write 0 to a dummy register before reading,
+         * and write back what we read. We must read/write the full 32-bit
+         * contents so we need to shift and mask by hand.
+         */
+        dummy = pa_pxp_cfg_addr(hose, bus->number, devfn, 0x10);
+        out_le32(dummy, 0);
+        tmp = in_le32(addr);
+        out_le32(addr, tmp);
+
+        switch (len) {
+        case 1:
+                *val = (tmp >> (8*byte)) & 0xff;
+                break;
+        case 2:
+                if (byte == 0)
+                        *val = tmp & 0xffff;
+                else
+                        *val = (tmp >> 16) & 0xffff;
+                break;
+        default:
+                *val = tmp;
+                break;
+        }
+
+        return 1;
+}
+
 static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
                               int offset, int len, u32 *val)
 {
@@ -64,6 +119,9 @@ static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
         if (!pa_pxp_offset_valid(bus->number, devfn, offset))
                 return PCIBIOS_BAD_REGISTER_NUMBER;
 
+        if (workaround_5945(bus, devfn, offset, len, val))
+                return PCIBIOS_SUCCESSFUL;
+
         addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
 
         /*
@@ -107,23 +165,20 @@ static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
         switch (len) {
         case 1:
                 out_8(addr, val);
-                (void) in_8(addr);
                 break;
         case 2:
                 out_le16(addr, val);
-                (void) in_le16(addr);
                 break;
         default:
                 out_le32(addr, val);
-                (void) in_le32(addr);
                 break;
         }
         return PCIBIOS_SUCCESSFUL;
 }
 
 static struct pci_ops pa_pxp_ops = {
-        pa_pxp_read_config,
-        pa_pxp_write_config,
+        .read = pa_pxp_read_config,
+        .write = pa_pxp_write_config,
 };
 
 static void __init setup_pa_pxp(struct pci_controller *hose)
@@ -178,3 +233,12 @@ void __init pas_pci_init(void)
         /* Use the common resource allocation mechanism */
         pci_probe_only = 1;
 }
+
+void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset)
+{
+        struct pci_controller *hose;
+
+        hose = pci_bus_to_host(dev->bus);
+
+        return (void __iomem *)pa_pxp_cfg_addr(hose, dev->bus->number, dev->devfn, offset);
+}
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index ffe6528048b5..5ddf40a66ae8 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -39,8 +39,21 @@
 
 #include "pasemi.h"
 
+/* SDC reset register, must be pre-mapped at reset time */
 static void __iomem *reset_reg;
 
+/* Various error status registers, must be pre-mapped at MCE time */
+
+#define MAX_MCE_REGS    32
+struct mce_regs {
+        char *name;
+        void __iomem *addr;
+};
+
+static struct mce_regs mce_regs[MAX_MCE_REGS];
+static int num_mce_regs;
+
+
 static void pas_restart(char *cmd)
 {
         printk("Restarting...\n");
@@ -50,26 +63,30 @@ static void pas_restart(char *cmd)
 
 #ifdef CONFIG_SMP
 static DEFINE_SPINLOCK(timebase_lock);
+static unsigned long timebase;
 
 static void __devinit pas_give_timebase(void)
 {
-        unsigned long tb;
-
         spin_lock(&timebase_lock);
         mtspr(SPRN_TBCTL, TBCTL_FREEZE);
-        tb = mftb();
-        mtspr(SPRN_TBCTL, TBCTL_UPDATE_LOWER | (tb & 0xffffffff));
-        mtspr(SPRN_TBCTL, TBCTL_UPDATE_UPPER | (tb >> 32));
-        mtspr(SPRN_TBCTL, TBCTL_RESTART);
+        isync();
+        timebase = get_tb();
         spin_unlock(&timebase_lock);
-        pr_debug("pas_give_timebase: cpu %d gave tb %lx\n",
-                 smp_processor_id(), tb);
+
+        while (timebase)
+                barrier();
+        mtspr(SPRN_TBCTL, TBCTL_RESTART);
 }
 
 static void __devinit pas_take_timebase(void)
 {
-        pr_debug("pas_take_timebase: cpu %d has tb %lx\n",
-                 smp_processor_id(), mftb());
+        while (!timebase)
+                smp_rmb();
+
+        spin_lock(&timebase_lock);
+        set_tb(timebase >> 32, timebase & 0xffffffff);
+        timebase = 0;
+        spin_unlock(&timebase_lock);
 }
 
 struct smp_ops_t pas_smp_ops = {
@@ -98,9 +115,60 @@ void __init pas_setup_arch(void)
         /* Remap SDC register for doing reset */
         /* XXXOJN This should maybe come out of the device tree */
         reset_reg = ioremap(0xfc101100, 4);
+}
+
+static int __init pas_setup_mce_regs(void)
+{
+        struct pci_dev *dev;
+        int reg;
+
+        if (!machine_is(pasemi))
+                return -ENODEV;
+
+        /* Remap various SoC status registers for use by the MCE handler */
+
+        reg = 0;
+
+        dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL);
+        while (dev && reg < MAX_MCE_REGS) {
+                mce_regs[reg].name = kasprintf(GFP_KERNEL,
+                                                "mc%d_mcdebug_errsta", reg);
+                mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730);
+                dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev);
+                reg++;
+        }
+
+        dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
+        if (dev && reg+4 < MAX_MCE_REGS) {
+                mce_regs[reg].name = "iobdbg_IntStatus1";
+                mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438);
+                reg++;
+                mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg";
+                mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454);
+                reg++;
+                mce_regs[reg].name = "iobiom_IntStatus";
+                mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10);
+                reg++;
+                mce_regs[reg].name = "iobiom_IntDbgReg";
+                mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c);
+                reg++;
+        }
+
+        dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL);
+        if (dev && reg+2 < MAX_MCE_REGS) {
+                mce_regs[reg].name = "l2csts_IntStatus";
+                mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200);
+                reg++;
+                mce_regs[reg].name = "l2csts_Cnt";
+                mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214);
+                reg++;
+        }
 
-        pasemi_idle_init();
+        num_mce_regs = reg;
+
+        return 0;
 }
+device_initcall(pas_setup_mce_regs);
 
 static __init void pas_init_IRQ(void)
 {
@@ -162,25 +230,34 @@ static int pas_machine_check_handler(struct pt_regs *regs)
 {
         int cpu = smp_processor_id();
         unsigned long srr0, srr1, dsisr;
+        int dump_slb = 0;
+        int i;
 
         srr0 = regs->nip;
         srr1 = regs->msr;
         dsisr = mfspr(SPRN_DSISR);
         printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
-        printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
-        printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar);
+        printk(KERN_ERR "SRR0  0x%016lx SRR1 0x%016lx\n", srr0, srr1);
+        printk(KERN_ERR "DSISR 0x%016lx DAR  0x%016lx\n", dsisr, regs->dar);
+        printk(KERN_ERR "BER   0x%016lx MER  0x%016lx\n", mfspr(SPRN_PA6T_BER),
+                mfspr(SPRN_PA6T_MER));
+        printk(KERN_ERR "IER   0x%016lx DER  0x%016lx\n", mfspr(SPRN_PA6T_IER),
+                mfspr(SPRN_PA6T_DER));
         printk(KERN_ERR "Cause:\n");
 
         if (srr1 & 0x200000)
                 printk(KERN_ERR "Signalled by SDC\n");
+
         if (srr1 & 0x100000) {
                 printk(KERN_ERR "Load/Store detected error:\n");
                 if (dsisr & 0x8000)
                         printk(KERN_ERR "D-cache ECC double-bit error or bus error\n");
                 if (dsisr & 0x4000)
                         printk(KERN_ERR "LSU snoop response error\n");
-                if (dsisr & 0x2000)
+                if (dsisr & 0x2000) {
                         printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n");
+                        dump_slb = 1;
+                }
                 if (dsisr & 0x1000)
                         printk(KERN_ERR "Recoverable Duptags\n");
                 if (dsisr & 0x800)
@@ -188,13 +265,40 @@ static int pas_machine_check_handler(struct pt_regs *regs)
                 if (dsisr & 0x400)
                         printk(KERN_ERR "TLB parity error count overflow\n");
         }
+
         if (srr1 & 0x80000)
                 printk(KERN_ERR "Bus Error\n");
-        if (srr1 & 0x40000)
+
+        if (srr1 & 0x40000) {
                 printk(KERN_ERR "I-side SLB multiple hit\n");
+                dump_slb = 1;
+        }
+
         if (srr1 & 0x20000)
                 printk(KERN_ERR "I-cache parity error hit\n");
 
+        if (num_mce_regs == 0)
+                printk(KERN_ERR "No MCE registers mapped yet, can't dump\n");
+        else
+                printk(KERN_ERR "SoC debug registers:\n");
+
+        for (i = 0; i < num_mce_regs; i++)
+                printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name,
+                        in_le32(mce_regs[i].addr));
+
+        if (dump_slb) {
+                unsigned long e, v;
+                int i;
+
+                printk(KERN_ERR "slb contents:\n");
+                for (i = 0; i < SLB_NUM_ENTRIES; i++) {
+                        asm volatile("slbmfee  %0,%1" : "=r" (e) : "r" (i));
+                        asm volatile("slbmfev  %0,%1" : "=r" (v) : "r" (i));
+                        printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v);
+                }
+        }
+
+
         /* SRR1[62] is from MSR[62] if recoverable, so pass that back */
         return !!(srr1 & 0x2);
 }