diff options
author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-23 01:11:30 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-23 01:11:30 -0400 |
commit | 45c091bb2d453ce4a8b06cf19872ec7a77fc4799 (patch) | |
tree | 06fb2e05518ebfba163f8424e028e7faf5672d66 /arch/powerpc/platforms/iseries/pci.c | |
parent | d588fcbe5a7ba8bba2cebf7799ab2d573717a806 (diff) | |
parent | 2191fe3e39159e3375f4b7ec1420df149f154101 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (139 commits)
[POWERPC] re-enable OProfile for iSeries, using timer interrupt
[POWERPC] support ibm,extended-*-frequency properties
[POWERPC] Extra sanity check in EEH code
[POWERPC] Dont look for class-code in pci children
[POWERPC] Fix mdelay badness on shared processor partitions
[POWERPC] disable floating point exceptions for init
[POWERPC] Unify ppc syscall tables
[POWERPC] mpic: add support for serial mode interrupts
[POWERPC] pseries: Print PCI slot location code on failure
[POWERPC] spufs: one more fix for 64k pages
[POWERPC] spufs: fail spu_create with invalid flags
[POWERPC] spufs: clear class2 interrupt status before wakeup
[POWERPC] spufs: fix Makefile for "make clean"
[POWERPC] spufs: remove stop_code from struct spu
[POWERPC] spufs: fix spu irq affinity setting
[POWERPC] spufs: further abstract priv1 register access
[POWERPC] spufs: split the Cell BE support into generic and platform dependant parts
[POWERPC] spufs: dont try to access SPE channel 1 count
[POWERPC] spufs: use kzalloc in create_spu
[POWERPC] spufs: fix initial state of wbox file
...
Manually resolved conflicts in:
drivers/net/phy/Makefile
include/asm-powerpc/spu.h
Diffstat (limited to 'arch/powerpc/platforms/iseries/pci.c')
-rw-r--r-- | arch/powerpc/platforms/iseries/pci.c | 347 |
1 files changed, 74 insertions, 273 deletions
diff --git a/arch/powerpc/platforms/iseries/pci.c b/arch/powerpc/platforms/iseries/pci.c index a19833b880e4..35bcc98111f5 100644 --- a/arch/powerpc/platforms/iseries/pci.c +++ b/arch/powerpc/platforms/iseries/pci.c | |||
@@ -37,36 +37,18 @@ | |||
37 | 37 | ||
38 | #include <asm/iseries/hv_call_xm.h> | 38 | #include <asm/iseries/hv_call_xm.h> |
39 | #include <asm/iseries/mf.h> | 39 | #include <asm/iseries/mf.h> |
40 | #include <asm/iseries/iommu.h> | ||
40 | 41 | ||
41 | #include <asm/ppc-pci.h> | 42 | #include <asm/ppc-pci.h> |
42 | 43 | ||
43 | #include "irq.h" | 44 | #include "irq.h" |
44 | #include "pci.h" | 45 | #include "pci.h" |
45 | #include "call_pci.h" | 46 | #include "call_pci.h" |
46 | #include "iommu.h" | ||
47 | |||
48 | extern unsigned long io_page_mask; | ||
49 | 47 | ||
50 | /* | 48 | /* |
51 | * Forward declares of prototypes. | 49 | * Forward declares of prototypes. |
52 | */ | 50 | */ |
53 | static struct device_node *find_Device_Node(int bus, int devfn); | 51 | static struct device_node *find_Device_Node(int bus, int devfn); |
54 | static void scan_PHB_slots(struct pci_controller *Phb); | ||
55 | static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel); | ||
56 | static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info); | ||
57 | |||
58 | LIST_HEAD(iSeries_Global_Device_List); | ||
59 | |||
60 | static int DeviceCount; | ||
61 | |||
62 | /* Counters and control flags. */ | ||
63 | static long Pci_Io_Read_Count; | ||
64 | static long Pci_Io_Write_Count; | ||
65 | #if 0 | ||
66 | static long Pci_Cfg_Read_Count; | ||
67 | static long Pci_Cfg_Write_Count; | ||
68 | #endif | ||
69 | static long Pci_Error_Count; | ||
70 | 52 | ||
71 | static int Pci_Retry_Max = 3; /* Only retry 3 times */ | 53 | static int Pci_Retry_Max = 3; /* Only retry 3 times */ |
72 | static int Pci_Error_Flag = 1; /* Set Retry Error on. */ | 54 | static int Pci_Error_Flag = 1; /* Set Retry Error on. */ |
@@ -81,41 +63,19 @@ static struct pci_ops iSeries_pci_ops; | |||
81 | #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL | 63 | #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL |
82 | #define BASE_IO_MEMORY 0xE000000000000000UL | 64 | #define BASE_IO_MEMORY 0xE000000000000000UL |
83 | 65 | ||
84 | static unsigned long max_io_memory = 0xE000000000000000UL; | 66 | static unsigned long max_io_memory = BASE_IO_MEMORY; |
85 | static long current_iomm_table_entry; | 67 | static long current_iomm_table_entry; |
86 | 68 | ||
87 | /* | 69 | /* |
88 | * Lookup Tables. | 70 | * Lookup Tables. |
89 | */ | 71 | */ |
90 | static struct device_node **iomm_table; | 72 | static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES]; |
91 | static u8 *iobar_table; | 73 | static u8 iobar_table[IOMM_TABLE_MAX_ENTRIES]; |
92 | 74 | ||
93 | /* | 75 | static const char pci_io_text[] = "iSeries PCI I/O"; |
94 | * Static and Global variables | ||
95 | */ | ||
96 | static char *pci_io_text = "iSeries PCI I/O"; | ||
97 | static DEFINE_SPINLOCK(iomm_table_lock); | 76 | static DEFINE_SPINLOCK(iomm_table_lock); |
98 | 77 | ||
99 | /* | 78 | /* |
100 | * iomm_table_initialize | ||
101 | * | ||
102 | * Allocates and initalizes the Address Translation Table and Bar | ||
103 | * Tables to get them ready for use. Must be called before any | ||
104 | * I/O space is handed out to the device BARs. | ||
105 | */ | ||
106 | static void iomm_table_initialize(void) | ||
107 | { | ||
108 | spin_lock(&iomm_table_lock); | ||
109 | iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES, | ||
110 | GFP_KERNEL); | ||
111 | iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES, | ||
112 | GFP_KERNEL); | ||
113 | spin_unlock(&iomm_table_lock); | ||
114 | if ((iomm_table == NULL) || (iobar_table == NULL)) | ||
115 | panic("PCI: I/O tables allocation failed.\n"); | ||
116 | } | ||
117 | |||
118 | /* | ||
119 | * iomm_table_allocate_entry | 79 | * iomm_table_allocate_entry |
120 | * | 80 | * |
121 | * Adds pci_dev entry in address translation table | 81 | * Adds pci_dev entry in address translation table |
@@ -142,9 +102,8 @@ static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) | |||
142 | */ | 102 | */ |
143 | spin_lock(&iomm_table_lock); | 103 | spin_lock(&iomm_table_lock); |
144 | bar_res->name = pci_io_text; | 104 | bar_res->name = pci_io_text; |
145 | bar_res->start = | 105 | bar_res->start = BASE_IO_MEMORY + |
146 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; | 106 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
147 | bar_res->start += BASE_IO_MEMORY; | ||
148 | bar_res->end = bar_res->start + bar_size - 1; | 107 | bar_res->end = bar_res->start + bar_size - 1; |
149 | /* | 108 | /* |
150 | * Allocate the number of table entries needed for BAR. | 109 | * Allocate the number of table entries needed for BAR. |
@@ -156,7 +115,7 @@ static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) | |||
156 | ++current_iomm_table_entry; | 115 | ++current_iomm_table_entry; |
157 | } | 116 | } |
158 | max_io_memory = BASE_IO_MEMORY + | 117 | max_io_memory = BASE_IO_MEMORY + |
159 | (IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry); | 118 | IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry; |
160 | spin_unlock(&iomm_table_lock); | 119 | spin_unlock(&iomm_table_lock); |
161 | } | 120 | } |
162 | 121 | ||
@@ -173,13 +132,10 @@ static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num) | |||
173 | */ | 132 | */ |
174 | static void allocate_device_bars(struct pci_dev *dev) | 133 | static void allocate_device_bars(struct pci_dev *dev) |
175 | { | 134 | { |
176 | struct resource *bar_res; | ||
177 | int bar_num; | 135 | int bar_num; |
178 | 136 | ||
179 | for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) { | 137 | for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) |
180 | bar_res = &dev->resource[bar_num]; | ||
181 | iomm_table_allocate_entry(dev, bar_num); | 138 | iomm_table_allocate_entry(dev, bar_num); |
182 | } | ||
183 | } | 139 | } |
184 | 140 | ||
185 | /* | 141 | /* |
@@ -199,34 +155,7 @@ static void pci_Log_Error(char *Error_Text, int Bus, int SubBus, | |||
199 | } | 155 | } |
200 | 156 | ||
201 | /* | 157 | /* |
202 | * build_device_node(u16 Bus, int SubBus, u8 DevFn) | 158 | * iSeries_pcibios_init |
203 | */ | ||
204 | static struct device_node *build_device_node(HvBusNumber Bus, | ||
205 | HvSubBusNumber SubBus, int AgentId, int Function) | ||
206 | { | ||
207 | struct device_node *node; | ||
208 | struct pci_dn *pdn; | ||
209 | |||
210 | node = kmalloc(sizeof(struct device_node), GFP_KERNEL); | ||
211 | if (node == NULL) | ||
212 | return NULL; | ||
213 | memset(node, 0, sizeof(struct device_node)); | ||
214 | pdn = kzalloc(sizeof(*pdn), GFP_KERNEL); | ||
215 | if (pdn == NULL) { | ||
216 | kfree(node); | ||
217 | return NULL; | ||
218 | } | ||
219 | node->data = pdn; | ||
220 | pdn->node = node; | ||
221 | list_add_tail(&pdn->Device_List, &iSeries_Global_Device_List); | ||
222 | pdn->busno = Bus; | ||
223 | pdn->bussubno = SubBus; | ||
224 | pdn->devfn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function); | ||
225 | return node; | ||
226 | } | ||
227 | |||
228 | /* | ||
229 | * unsigned long __init find_and_init_phbs(void) | ||
230 | * | 159 | * |
231 | * Description: | 160 | * Description: |
232 | * This function checks for all possible system PCI host bridges that connect | 161 | * This function checks for all possible system PCI host bridges that connect |
@@ -234,50 +163,42 @@ static struct device_node *build_device_node(HvBusNumber Bus, | |||
234 | * ownership status. A pci_controller is built for any bus which is partially | 163 | * ownership status. A pci_controller is built for any bus which is partially |
235 | * owned or fully owned by this guest partition. | 164 | * owned or fully owned by this guest partition. |
236 | */ | 165 | */ |
237 | unsigned long __init find_and_init_phbs(void) | 166 | void iSeries_pcibios_init(void) |
238 | { | 167 | { |
239 | struct pci_controller *phb; | 168 | struct pci_controller *phb; |
240 | HvBusNumber bus; | 169 | struct device_node *root = of_find_node_by_path("/"); |
241 | 170 | struct device_node *node = NULL; | |
242 | /* Check all possible buses. */ | ||
243 | for (bus = 0; bus < 256; bus++) { | ||
244 | int ret = HvCallXm_testBus(bus); | ||
245 | if (ret == 0) { | ||
246 | printk("bus %d appears to exist\n", bus); | ||
247 | 171 | ||
248 | phb = pcibios_alloc_controller(NULL); | 172 | if (root == NULL) { |
249 | if (phb == NULL) | 173 | printk(KERN_CRIT "iSeries_pcibios_init: can't find root " |
250 | return -ENOMEM; | 174 | "of device tree\n"); |
251 | 175 | return; | |
252 | phb->pci_mem_offset = phb->local_number = bus; | 176 | } |
253 | phb->first_busno = bus; | 177 | while ((node = of_get_next_child(root, node)) != NULL) { |
254 | phb->last_busno = bus; | 178 | HvBusNumber bus; |
255 | phb->ops = &iSeries_pci_ops; | 179 | u32 *busp; |
256 | 180 | ||
257 | /* Find and connect the devices. */ | 181 | if ((node->type == NULL) || (strcmp(node->type, "pci") != 0)) |
258 | scan_PHB_slots(phb); | 182 | continue; |
259 | } | 183 | |
260 | /* | 184 | busp = (u32 *)get_property(node, "bus-range", NULL); |
261 | * Check for Unexpected Return code, a clue that something | 185 | if (busp == NULL) |
262 | * has gone wrong. | 186 | continue; |
263 | */ | 187 | bus = *busp; |
264 | else if (ret != 0x0301) | 188 | printk("bus %d appears to exist\n", bus); |
265 | printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X", | 189 | phb = pcibios_alloc_controller(node); |
266 | bus, ret); | 190 | if (phb == NULL) |
191 | continue; | ||
192 | |||
193 | phb->pci_mem_offset = phb->local_number = bus; | ||
194 | phb->first_busno = bus; | ||
195 | phb->last_busno = bus; | ||
196 | phb->ops = &iSeries_pci_ops; | ||
267 | } | 197 | } |
268 | return 0; | ||
269 | } | ||
270 | 198 | ||
271 | /* | 199 | of_node_put(root); |
272 | * iSeries_pcibios_init | 200 | |
273 | * | 201 | pci_devs_phb_init(); |
274 | * Chance to initialize and structures or variable before PCI Bus walk. | ||
275 | */ | ||
276 | void iSeries_pcibios_init(void) | ||
277 | { | ||
278 | iomm_table_initialize(); | ||
279 | find_and_init_phbs(); | ||
280 | io_page_mask = -1; | ||
281 | } | 202 | } |
282 | 203 | ||
283 | /* | 204 | /* |
@@ -299,6 +220,34 @@ void __init iSeries_pci_final_fixup(void) | |||
299 | pdev->bus->number, pdev->devfn, node); | 220 | pdev->bus->number, pdev->devfn, node); |
300 | 221 | ||
301 | if (node != NULL) { | 222 | if (node != NULL) { |
223 | struct pci_dn *pdn = PCI_DN(node); | ||
224 | u32 *agent; | ||
225 | |||
226 | agent = (u32 *)get_property(node, "linux,agent-id", | ||
227 | NULL); | ||
228 | if ((pdn != NULL) && (agent != NULL)) { | ||
229 | u8 irq = iSeries_allocate_IRQ(pdn->busno, 0, | ||
230 | pdn->bussubno); | ||
231 | int err; | ||
232 | |||
233 | err = HvCallXm_connectBusUnit(pdn->busno, pdn->bussubno, | ||
234 | *agent, irq); | ||
235 | if (err) | ||
236 | pci_Log_Error("Connect Bus Unit", | ||
237 | pdn->busno, pdn->bussubno, *agent, err); | ||
238 | else { | ||
239 | err = HvCallPci_configStore8(pdn->busno, pdn->bussubno, | ||
240 | *agent, | ||
241 | PCI_INTERRUPT_LINE, | ||
242 | irq); | ||
243 | if (err) | ||
244 | pci_Log_Error("PciCfgStore Irq Failed!", | ||
245 | pdn->busno, pdn->bussubno, *agent, err); | ||
246 | } | ||
247 | if (!err) | ||
248 | pdev->irq = irq; | ||
249 | } | ||
250 | |||
302 | ++DeviceCount; | 251 | ++DeviceCount; |
303 | pdev->sysdata = (void *)node; | 252 | pdev->sysdata = (void *)node; |
304 | PCI_DN(node)->pcidev = pdev; | 253 | PCI_DN(node)->pcidev = pdev; |
@@ -308,7 +257,6 @@ void __init iSeries_pci_final_fixup(void) | |||
308 | } else | 257 | } else |
309 | printk("PCI: Device Tree not found for 0x%016lX\n", | 258 | printk("PCI: Device Tree not found for 0x%016lX\n", |
310 | (unsigned long)pdev); | 259 | (unsigned long)pdev); |
311 | pdev->irq = PCI_DN(node)->Irq; | ||
312 | } | 260 | } |
313 | iSeries_activate_IRQs(); | 261 | iSeries_activate_IRQs(); |
314 | mf_display_src(0xC9000200); | 262 | mf_display_src(0xC9000200); |
@@ -323,148 +271,6 @@ void pcibios_fixup_resources(struct pci_dev *pdev) | |||
323 | } | 271 | } |
324 | 272 | ||
325 | /* | 273 | /* |
326 | * Loop through each node function to find usable EADs bridges. | ||
327 | */ | ||
328 | static void scan_PHB_slots(struct pci_controller *Phb) | ||
329 | { | ||
330 | struct HvCallPci_DeviceInfo *DevInfo; | ||
331 | HvBusNumber bus = Phb->local_number; /* System Bus */ | ||
332 | const HvSubBusNumber SubBus = 0; /* EADs is always 0. */ | ||
333 | int HvRc = 0; | ||
334 | int IdSel; | ||
335 | const int MaxAgents = 8; | ||
336 | |||
337 | DevInfo = (struct HvCallPci_DeviceInfo*) | ||
338 | kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL); | ||
339 | if (DevInfo == NULL) | ||
340 | return; | ||
341 | |||
342 | /* | ||
343 | * Probe for EADs Bridges | ||
344 | */ | ||
345 | for (IdSel = 1; IdSel < MaxAgents; ++IdSel) { | ||
346 | HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel, | ||
347 | iseries_hv_addr(DevInfo), | ||
348 | sizeof(struct HvCallPci_DeviceInfo)); | ||
349 | if (HvRc == 0) { | ||
350 | if (DevInfo->deviceType == HvCallPci_NodeDevice) | ||
351 | scan_EADS_bridge(bus, SubBus, IdSel); | ||
352 | else | ||
353 | printk("PCI: Invalid System Configuration(0x%02X)" | ||
354 | " for bus 0x%02x id 0x%02x.\n", | ||
355 | DevInfo->deviceType, bus, IdSel); | ||
356 | } | ||
357 | else | ||
358 | pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc); | ||
359 | } | ||
360 | kfree(DevInfo); | ||
361 | } | ||
362 | |||
363 | static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus, | ||
364 | int IdSel) | ||
365 | { | ||
366 | struct HvCallPci_BridgeInfo *BridgeInfo; | ||
367 | HvAgentId AgentId; | ||
368 | int Function; | ||
369 | int HvRc; | ||
370 | |||
371 | BridgeInfo = (struct HvCallPci_BridgeInfo *) | ||
372 | kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL); | ||
373 | if (BridgeInfo == NULL) | ||
374 | return; | ||
375 | |||
376 | /* Note: hvSubBus and irq is always be 0 at this level! */ | ||
377 | for (Function = 0; Function < 8; ++Function) { | ||
378 | AgentId = ISERIES_PCI_AGENTID(IdSel, Function); | ||
379 | HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0); | ||
380 | if (HvRc == 0) { | ||
381 | printk("found device at bus %d idsel %d func %d (AgentId %x)\n", | ||
382 | bus, IdSel, Function, AgentId); | ||
383 | /* Connect EADs: 0x18.00.12 = 0x00 */ | ||
384 | HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId, | ||
385 | iseries_hv_addr(BridgeInfo), | ||
386 | sizeof(struct HvCallPci_BridgeInfo)); | ||
387 | if (HvRc == 0) { | ||
388 | printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n", | ||
389 | BridgeInfo->busUnitInfo.deviceType, | ||
390 | BridgeInfo->subBusNumber, | ||
391 | BridgeInfo->maxAgents, | ||
392 | BridgeInfo->maxSubBusNumber, | ||
393 | BridgeInfo->logicalSlotNumber); | ||
394 | if (BridgeInfo->busUnitInfo.deviceType == | ||
395 | HvCallPci_BridgeDevice) { | ||
396 | /* Scan_Bridge_Slot...: 0x18.00.12 */ | ||
397 | scan_bridge_slot(bus, BridgeInfo); | ||
398 | } else | ||
399 | printk("PCI: Invalid Bridge Configuration(0x%02X)", | ||
400 | BridgeInfo->busUnitInfo.deviceType); | ||
401 | } | ||
402 | } else if (HvRc != 0x000B) | ||
403 | pci_Log_Error("EADs Connect", | ||
404 | bus, SubBus, AgentId, HvRc); | ||
405 | } | ||
406 | kfree(BridgeInfo); | ||
407 | } | ||
408 | |||
409 | /* | ||
410 | * This assumes that the node slot is always on the primary bus! | ||
411 | */ | ||
412 | static int scan_bridge_slot(HvBusNumber Bus, | ||
413 | struct HvCallPci_BridgeInfo *BridgeInfo) | ||
414 | { | ||
415 | struct device_node *node; | ||
416 | HvSubBusNumber SubBus = BridgeInfo->subBusNumber; | ||
417 | u16 VendorId = 0; | ||
418 | int HvRc = 0; | ||
419 | u8 Irq = 0; | ||
420 | int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus); | ||
421 | int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus); | ||
422 | HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function); | ||
423 | |||
424 | /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */ | ||
425 | Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel); | ||
426 | |||
427 | /* | ||
428 | * Connect all functions of any device found. | ||
429 | */ | ||
430 | for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) { | ||
431 | for (Function = 0; Function < 8; ++Function) { | ||
432 | HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function); | ||
433 | HvRc = HvCallXm_connectBusUnit(Bus, SubBus, | ||
434 | AgentId, Irq); | ||
435 | if (HvRc != 0) { | ||
436 | pci_Log_Error("Connect Bus Unit", | ||
437 | Bus, SubBus, AgentId, HvRc); | ||
438 | continue; | ||
439 | } | ||
440 | |||
441 | HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId, | ||
442 | PCI_VENDOR_ID, &VendorId); | ||
443 | if (HvRc != 0) { | ||
444 | pci_Log_Error("Read Vendor", | ||
445 | Bus, SubBus, AgentId, HvRc); | ||
446 | continue; | ||
447 | } | ||
448 | printk("read vendor ID: %x\n", VendorId); | ||
449 | |||
450 | /* FoundDevice: 0x18.28.10 = 0x12AE */ | ||
451 | HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId, | ||
452 | PCI_INTERRUPT_LINE, Irq); | ||
453 | if (HvRc != 0) | ||
454 | pci_Log_Error("PciCfgStore Irq Failed!", | ||
455 | Bus, SubBus, AgentId, HvRc); | ||
456 | |||
457 | ++DeviceCount; | ||
458 | node = build_device_node(Bus, SubBus, EADsIdSel, Function); | ||
459 | PCI_DN(node)->Irq = Irq; | ||
460 | PCI_DN(node)->LogicalSlot = BridgeInfo->logicalSlotNumber; | ||
461 | |||
462 | } /* for (Function = 0; Function < 8; ++Function) */ | ||
463 | } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */ | ||
464 | return HvRc; | ||
465 | } | ||
466 | |||
467 | /* | ||
468 | * I/0 Memory copy MUST use mmio commands on iSeries | 274 | * I/0 Memory copy MUST use mmio commands on iSeries |
469 | * To do; For performance, include the hv call directly | 275 | * To do; For performance, include the hv call directly |
470 | */ | 276 | */ |
@@ -509,11 +315,13 @@ EXPORT_SYMBOL(iSeries_memcpy_fromio); | |||
509 | */ | 315 | */ |
510 | static struct device_node *find_Device_Node(int bus, int devfn) | 316 | static struct device_node *find_Device_Node(int bus, int devfn) |
511 | { | 317 | { |
512 | struct pci_dn *pdn; | 318 | struct device_node *node; |
319 | |||
320 | for (node = NULL; (node = of_find_all_nodes(node)); ) { | ||
321 | struct pci_dn *pdn = PCI_DN(node); | ||
513 | 322 | ||
514 | list_for_each_entry(pdn, &iSeries_Global_Device_List, Device_List) { | 323 | if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn)) |
515 | if ((bus == pdn->busno) && (devfn == pdn->devfn)) | 324 | return node; |
516 | return pdn->node; | ||
517 | } | 325 | } |
518 | return NULL; | 326 | return NULL; |
519 | } | 327 | } |
@@ -625,7 +433,6 @@ static int CheckReturnCode(char *TextHdr, struct device_node *DevNode, | |||
625 | if (ret != 0) { | 433 | if (ret != 0) { |
626 | struct pci_dn *pdn = PCI_DN(DevNode); | 434 | struct pci_dn *pdn = PCI_DN(DevNode); |
627 | 435 | ||
628 | ++Pci_Error_Count; | ||
629 | (*retry)++; | 436 | (*retry)++; |
630 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", | 437 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", |
631 | TextHdr, pdn->busno, pdn->devfn, | 438 | TextHdr, pdn->busno, pdn->devfn, |
@@ -707,7 +514,6 @@ u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress) | |||
707 | return 0xff; | 514 | return 0xff; |
708 | } | 515 | } |
709 | do { | 516 | do { |
710 | ++Pci_Io_Read_Count; | ||
711 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0); | 517 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0); |
712 | } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0); | 518 | } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0); |
713 | 519 | ||
@@ -737,7 +543,6 @@ u16 iSeries_Read_Word(const volatile void __iomem *IoAddress) | |||
737 | return 0xffff; | 543 | return 0xffff; |
738 | } | 544 | } |
739 | do { | 545 | do { |
740 | ++Pci_Io_Read_Count; | ||
741 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, | 546 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, |
742 | BarOffset, 0); | 547 | BarOffset, 0); |
743 | } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0); | 548 | } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0); |
@@ -768,7 +573,6 @@ u32 iSeries_Read_Long(const volatile void __iomem *IoAddress) | |||
768 | return 0xffffffff; | 573 | return 0xffffffff; |
769 | } | 574 | } |
770 | do { | 575 | do { |
771 | ++Pci_Io_Read_Count; | ||
772 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, | 576 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, |
773 | BarOffset, 0); | 577 | BarOffset, 0); |
774 | } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0); | 578 | } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0); |
@@ -806,7 +610,6 @@ void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress) | |||
806 | return; | 610 | return; |
807 | } | 611 | } |
808 | do { | 612 | do { |
809 | ++Pci_Io_Write_Count; | ||
810 | rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0); | 613 | rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0); |
811 | } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0); | 614 | } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0); |
812 | } | 615 | } |
@@ -834,7 +637,6 @@ void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress) | |||
834 | return; | 637 | return; |
835 | } | 638 | } |
836 | do { | 639 | do { |
837 | ++Pci_Io_Write_Count; | ||
838 | rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0); | 640 | rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0); |
839 | } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0); | 641 | } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0); |
840 | } | 642 | } |
@@ -862,7 +664,6 @@ void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress) | |||
862 | return; | 664 | return; |
863 | } | 665 | } |
864 | do { | 666 | do { |
865 | ++Pci_Io_Write_Count; | ||
866 | rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0); | 667 | rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0); |
867 | } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0); | 668 | } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0); |
868 | } | 669 | } |