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authorIshizaki Kou <kou.ishizaki@toshiba.co.jp>2008-04-24 05:26:28 -0400
committerPaul Mackerras <paulus@samba.org>2008-04-24 07:08:13 -0400
commit11eef455c2834e192c6ffe9f3ffd09af70fafe81 (patch)
tree199940f8ca3f83c58f2cec2ffdef3ad9c8829921 /arch/powerpc/platforms/celleb
parent116bdc425c7e01e97cff2f3e6d0134511e8f13e3 (diff)
[POWERPC] celleb: Move the SCC related code for celleb
This moves the SCC (Super Companion Chip) related code for celleb into platforms/cell/. All files in this patch are used by celleb-beat and celleb-native commonly. Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/celleb')
-rw-r--r--arch/powerpc/platforms/celleb/Makefile4
-rw-r--r--arch/powerpc/platforms/celleb/scc.h145
-rw-r--r--arch/powerpc/platforms/celleb/scc_epci.c444
-rw-r--r--arch/powerpc/platforms/celleb/scc_sio.c101
-rw-r--r--arch/powerpc/platforms/celleb/scc_uhc.c95
5 files changed, 1 insertions, 788 deletions
diff --git a/arch/powerpc/platforms/celleb/Makefile b/arch/powerpc/platforms/celleb/Makefile
index 5b1096b40afb..edb6d5e858a1 100644
--- a/arch/powerpc/platforms/celleb/Makefile
+++ b/arch/powerpc/platforms/celleb/Makefile
@@ -1,8 +1,6 @@
1obj-y += interrupt.o iommu.o \ 1obj-y += interrupt.o iommu.o \
2 htab.o beat.o hvCall.o \ 2 htab.o beat.o hvCall.o
3 scc_epci.o scc_uhc.o
4 3
5obj-$(CONFIG_SMP) += smp.o 4obj-$(CONFIG_SMP) += smp.o
6obj-$(CONFIG_PPC_UDBG_BEAT) += udbg_beat.o 5obj-$(CONFIG_PPC_UDBG_BEAT) += udbg_beat.o
7obj-$(CONFIG_SERIAL_TXX9) += scc_sio.o
8obj-$(CONFIG_SPU_BASE) += spu_priv1.o 6obj-$(CONFIG_SPU_BASE) += spu_priv1.o
diff --git a/arch/powerpc/platforms/celleb/scc.h b/arch/powerpc/platforms/celleb/scc.h
deleted file mode 100644
index 6be1542a6e66..000000000000
--- a/arch/powerpc/platforms/celleb/scc.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * SCC (Super Companion Chip) definitions
3 *
4 * (C) Copyright 2004-2006 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef _CELLEB_SCC_H
22#define _CELLEB_SCC_H
23
24#define PCI_VENDOR_ID_TOSHIBA_2 0x102f
25#define PCI_DEVICE_ID_TOSHIBA_SCC_PCIEXC_BRIDGE 0x01b0
26#define PCI_DEVICE_ID_TOSHIBA_SCC_EPCI_BRIDGE 0x01b1
27#define PCI_DEVICE_ID_TOSHIBA_SCC_BRIDGE 0x01b2
28#define PCI_DEVICE_ID_TOSHIBA_SCC_GBE 0x01b3
29#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
30#define PCI_DEVICE_ID_TOSHIBA_SCC_USB2 0x01b5
31#define PCI_DEVICE_ID_TOSHIBA_SCC_USB 0x01b6
32#define PCI_DEVICE_ID_TOSHIBA_SCC_ENCDEC 0x01b7
33
34#define SCC_EPCI_REG 0x0000d000
35
36/* EPCI registers */
37#define SCC_EPCI_CNF10_REG 0x010
38#define SCC_EPCI_CNF14_REG 0x014
39#define SCC_EPCI_CNF18_REG 0x018
40#define SCC_EPCI_PVBAT 0x100
41#define SCC_EPCI_VPMBAT 0x104
42#define SCC_EPCI_VPIBAT 0x108
43#define SCC_EPCI_VCSR 0x110
44#define SCC_EPCI_VIENAB 0x114
45#define SCC_EPCI_VISTAT 0x118
46#define SCC_EPCI_VRDCOUNT 0x124
47#define SCC_EPCI_BAM0 0x12c
48#define SCC_EPCI_BAM1 0x134
49#define SCC_EPCI_BAM2 0x13c
50#define SCC_EPCI_IADR 0x164
51#define SCC_EPCI_CLKRST 0x800
52#define SCC_EPCI_INTSET 0x804
53#define SCC_EPCI_STATUS 0x808
54#define SCC_EPCI_ABTSET 0x80c
55#define SCC_EPCI_WATRP 0x810
56#define SCC_EPCI_DUMYRADR 0x814
57#define SCC_EPCI_SWRESP 0x818
58#define SCC_EPCI_CNTOPT 0x81c
59#define SCC_EPCI_ECMODE 0xf00
60#define SCC_EPCI_IOM_AC_NUM 5
61#define SCC_EPCI_IOM_ACTE(n) (0xf10 + (n) * 4)
62#define SCC_EPCI_IOT_AC_NUM 4
63#define SCC_EPCI_IOT_ACTE(n) (0xf30 + (n) * 4)
64#define SCC_EPCI_MAEA 0xf50
65#define SCC_EPCI_MAEC 0xf54
66#define SCC_EPCI_CKCTRL 0xff0
67
68/* bits for SCC_EPCI_VCSR */
69#define SCC_EPCI_VCSR_FRE 0x00020000
70#define SCC_EPCI_VCSR_FWE 0x00010000
71#define SCC_EPCI_VCSR_DR 0x00000400
72#define SCC_EPCI_VCSR_SR 0x00000008
73#define SCC_EPCI_VCSR_AT 0x00000004
74
75/* bits for SCC_EPCI_VIENAB/SCC_EPCI_VISTAT */
76#define SCC_EPCI_VISTAT_PMPE 0x00000008
77#define SCC_EPCI_VISTAT_PMFE 0x00000004
78#define SCC_EPCI_VISTAT_PRA 0x00000002
79#define SCC_EPCI_VISTAT_PRD 0x00000001
80#define SCC_EPCI_VISTAT_ALL 0x0000000f
81
82#define SCC_EPCI_VIENAB_PMPEE 0x00000008
83#define SCC_EPCI_VIENAB_PMFEE 0x00000004
84#define SCC_EPCI_VIENAB_PRA 0x00000002
85#define SCC_EPCI_VIENAB_PRD 0x00000001
86#define SCC_EPCI_VIENAB_ALL 0x0000000f
87
88/* bits for SCC_EPCI_CLKRST */
89#define SCC_EPCI_CLKRST_CKS_MASK 0x00030000
90#define SCC_EPCI_CLKRST_CKS_2 0x00000000
91#define SCC_EPCI_CLKRST_CKS_4 0x00010000
92#define SCC_EPCI_CLKRST_CKS_8 0x00020000
93#define SCC_EPCI_CLKRST_PCICRST 0x00000400
94#define SCC_EPCI_CLKRST_BC 0x00000200
95#define SCC_EPCI_CLKRST_PCIRST 0x00000100
96#define SCC_EPCI_CLKRST_PCKEN 0x00000001
97
98/* bits for SCC_EPCI_INTSET/SCC_EPCI_STATUS */
99#define SCC_EPCI_INT_2M 0x01000000
100#define SCC_EPCI_INT_RERR 0x00200000
101#define SCC_EPCI_INT_SERR 0x00100000
102#define SCC_EPCI_INT_PRTER 0x00080000
103#define SCC_EPCI_INT_SER 0x00040000
104#define SCC_EPCI_INT_PER 0x00020000
105#define SCC_EPCI_INT_PAI 0x00010000
106#define SCC_EPCI_INT_1M 0x00000100
107#define SCC_EPCI_INT_PME 0x00000010
108#define SCC_EPCI_INT_INTD 0x00000008
109#define SCC_EPCI_INT_INTC 0x00000004
110#define SCC_EPCI_INT_INTB 0x00000002
111#define SCC_EPCI_INT_INTA 0x00000001
112#define SCC_EPCI_INT_DEVINT 0x0000000f
113#define SCC_EPCI_INT_ALL 0x003f001f
114#define SCC_EPCI_INT_ALLERR 0x003f0000
115
116/* bits for SCC_EPCI_CKCTRL */
117#define SCC_EPCI_CKCTRL_CRST0 0x00010000
118#define SCC_EPCI_CKCTRL_CRST1 0x00020000
119#define SCC_EPCI_CKCTRL_OCLKEN 0x00000100
120#define SCC_EPCI_CKCTRL_LCLKEN 0x00000001
121
122#define SCC_EPCI_IDSEL_AD_TO_SLOT(ad) ((ad) - 10)
123#define SCC_EPCI_MAX_DEVNU SCC_EPCI_IDSEL_AD_TO_SLOT(32)
124
125/* bits for SCC_EPCI_CNTOPT */
126#define SCC_EPCI_CNTOPT_O2PMB 0x00000002
127
128/* UHC registers */
129#define SCC_UHC_CKRCTRL 0xff0
130#define SCC_UHC_ECMODE 0xf00
131
132/* bits for SCC_UHC_CKRCTRL */
133#define SCC_UHC_F48MCKLEN 0x00000001
134#define SCC_UHC_P_SUSPEND 0x00000002
135#define SCC_UHC_PHY_SUSPEND_SEL 0x00000004
136#define SCC_UHC_HCLKEN 0x00000100
137#define SCC_UHC_USBEN 0x00010000
138#define SCC_UHC_USBCEN 0x00020000
139#define SCC_UHC_PHYEN 0x00040000
140
141/* bits for SCC_UHC_ECMODE */
142#define SCC_UHC_ECMODE_BY_BYTE 0x00000555
143#define SCC_UHC_ECMODE_BY_WORD 0x00000aaa
144
145#endif /* _CELLEB_SCC_H */
diff --git a/arch/powerpc/platforms/celleb/scc_epci.c b/arch/powerpc/platforms/celleb/scc_epci.c
deleted file mode 100644
index 3f7aef947633..000000000000
--- a/arch/powerpc/platforms/celleb/scc_epci.c
+++ /dev/null
@@ -1,444 +0,0 @@
1/*
2 * Support for SCC external PCI
3 *
4 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#undef DEBUG
22
23#include <linux/kernel.h>
24#include <linux/threads.h>
25#include <linux/pci.h>
26#include <linux/init.h>
27#include <linux/pci_regs.h>
28#include <linux/bootmem.h>
29
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/prom.h>
33#include <asm/machdep.h>
34#include <asm/pci-bridge.h>
35#include <asm/ppc-pci.h>
36
37#include "scc.h"
38#include "../cell/celleb_pci.h"
39#include "interrupt.h"
40
41#define MAX_PCI_DEVICES 32
42#define MAX_PCI_FUNCTIONS 8
43
44#define iob() __asm__ __volatile__("eieio; sync":::"memory")
45
46static inline PCI_IO_ADDR celleb_epci_get_epci_base(
47 struct pci_controller *hose)
48{
49 /*
50 * Note:
51 * Celleb epci uses cfg_addr as a base address for
52 * epci control registers.
53 */
54
55 return hose->cfg_addr;
56}
57
58static inline PCI_IO_ADDR celleb_epci_get_epci_cfg(
59 struct pci_controller *hose)
60{
61 /*
62 * Note:
63 * Celleb epci uses cfg_data as a base address for
64 * configuration area for epci devices.
65 */
66
67 return hose->cfg_data;
68}
69
70static inline void clear_and_disable_master_abort_interrupt(
71 struct pci_controller *hose)
72{
73 PCI_IO_ADDR epci_base;
74 PCI_IO_ADDR reg;
75 epci_base = celleb_epci_get_epci_base(hose);
76 reg = epci_base + PCI_COMMAND;
77 out_be32(reg, in_be32(reg) | (PCI_STATUS_REC_MASTER_ABORT << 16));
78}
79
80static int celleb_epci_check_abort(struct pci_controller *hose,
81 PCI_IO_ADDR addr)
82{
83 PCI_IO_ADDR reg;
84 PCI_IO_ADDR epci_base;
85 u32 val;
86
87 iob();
88 epci_base = celleb_epci_get_epci_base(hose);
89
90 reg = epci_base + PCI_COMMAND;
91 val = in_be32(reg);
92
93 if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
94 out_be32(reg,
95 (val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
96
97 /* clear PCI Controller error, FRE, PMFE */
98 reg = epci_base + SCC_EPCI_STATUS;
99 out_be32(reg, SCC_EPCI_INT_PAI);
100
101 reg = epci_base + SCC_EPCI_VCSR;
102 val = in_be32(reg) & 0xffff;
103 val |= SCC_EPCI_VCSR_FRE;
104 out_be32(reg, val);
105
106 reg = epci_base + SCC_EPCI_VISTAT;
107 out_be32(reg, SCC_EPCI_VISTAT_PMFE);
108 return PCIBIOS_DEVICE_NOT_FOUND;
109 }
110
111 return PCIBIOS_SUCCESSFUL;
112}
113
114static PCI_IO_ADDR celleb_epci_make_config_addr(
115 struct pci_bus *bus,
116 struct pci_controller *hose,
117 unsigned int devfn, int where)
118{
119 PCI_IO_ADDR addr;
120
121 if (bus != hose->bus)
122 addr = celleb_epci_get_epci_cfg(hose) +
123 (((bus->number & 0xff) << 16)
124 | ((devfn & 0xff) << 8)
125 | (where & 0xff)
126 | 0x01000000);
127 else
128 addr = celleb_epci_get_epci_cfg(hose) +
129 (((devfn & 0xff) << 8) | (where & 0xff));
130
131 pr_debug("EPCI: config_addr = 0x%p\n", addr);
132
133 return addr;
134}
135
136static int celleb_epci_read_config(struct pci_bus *bus,
137 unsigned int devfn, int where, int size, u32 *val)
138{
139 PCI_IO_ADDR epci_base;
140 PCI_IO_ADDR addr;
141 struct device_node *node;
142 struct pci_controller *hose;
143
144 /* allignment check */
145 BUG_ON(where % size);
146
147 node = (struct device_node *)bus->sysdata;
148 hose = pci_find_hose_for_OF_device(node);
149
150 if (!celleb_epci_get_epci_cfg(hose))
151 return PCIBIOS_DEVICE_NOT_FOUND;
152
153 if (bus->number == hose->first_busno && devfn == 0) {
154 /* EPCI controller self */
155
156 epci_base = celleb_epci_get_epci_base(hose);
157 addr = epci_base + where;
158
159 switch (size) {
160 case 1:
161 *val = in_8(addr);
162 break;
163 case 2:
164 *val = in_be16(addr);
165 break;
166 case 4:
167 *val = in_be32(addr);
168 break;
169 default:
170 return PCIBIOS_DEVICE_NOT_FOUND;
171 }
172
173 } else {
174
175 clear_and_disable_master_abort_interrupt(hose);
176 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
177
178 switch (size) {
179 case 1:
180 *val = in_8(addr);
181 break;
182 case 2:
183 *val = in_le16(addr);
184 break;
185 case 4:
186 *val = in_le32(addr);
187 break;
188 default:
189 return PCIBIOS_DEVICE_NOT_FOUND;
190 }
191 }
192
193 pr_debug("EPCI: "
194 "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
195 addr, devfn, where, size, *val);
196
197 return celleb_epci_check_abort(hose, NULL);
198}
199
200static int celleb_epci_write_config(struct pci_bus *bus,
201 unsigned int devfn, int where, int size, u32 val)
202{
203 PCI_IO_ADDR epci_base;
204 PCI_IO_ADDR addr;
205 struct device_node *node;
206 struct pci_controller *hose;
207
208 /* allignment check */
209 BUG_ON(where % size);
210
211 node = (struct device_node *)bus->sysdata;
212 hose = pci_find_hose_for_OF_device(node);
213
214
215 if (!celleb_epci_get_epci_cfg(hose))
216 return PCIBIOS_DEVICE_NOT_FOUND;
217
218 if (bus->number == hose->first_busno && devfn == 0) {
219 /* EPCI controller self */
220
221 epci_base = celleb_epci_get_epci_base(hose);
222 addr = epci_base + where;
223
224 switch (size) {
225 case 1:
226 out_8(addr, val);
227 break;
228 case 2:
229 out_be16(addr, val);
230 break;
231 case 4:
232 out_be32(addr, val);
233 break;
234 default:
235 return PCIBIOS_DEVICE_NOT_FOUND;
236 }
237
238 } else {
239
240 clear_and_disable_master_abort_interrupt(hose);
241 addr = celleb_epci_make_config_addr(bus, hose, devfn, where);
242
243 switch (size) {
244 case 1:
245 out_8(addr, val);
246 break;
247 case 2:
248 out_le16(addr, val);
249 break;
250 case 4:
251 out_le32(addr, val);
252 break;
253 default:
254 return PCIBIOS_DEVICE_NOT_FOUND;
255 }
256 }
257
258 return celleb_epci_check_abort(hose, addr);
259}
260
261struct pci_ops celleb_epci_ops = {
262 .read = celleb_epci_read_config,
263 .write = celleb_epci_write_config,
264};
265
266/* to be moved in FW */
267static int __init celleb_epci_init(struct pci_controller *hose)
268{
269 u32 val;
270 PCI_IO_ADDR reg;
271 PCI_IO_ADDR epci_base;
272 int hwres = 0;
273
274 epci_base = celleb_epci_get_epci_base(hose);
275
276 /* PCI core reset(Internal bus and PCI clock) */
277 reg = epci_base + SCC_EPCI_CKCTRL;
278 val = in_be32(reg);
279 if (val == 0x00030101)
280 hwres = 1;
281 else {
282 val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
283 out_be32(reg, val);
284
285 /* set PCI core clock */
286 val = in_be32(reg);
287 val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
288 out_be32(reg, val);
289
290 /* release PCI core reset (internal bus) */
291 val = in_be32(reg);
292 val |= SCC_EPCI_CKCTRL_CRST0;
293 out_be32(reg, val);
294
295 /* set PCI clock select */
296 reg = epci_base + SCC_EPCI_CLKRST;
297 val = in_be32(reg);
298 val &= ~SCC_EPCI_CLKRST_CKS_MASK;
299 val |= SCC_EPCI_CLKRST_CKS_2;
300 out_be32(reg, val);
301
302 /* set arbiter */
303 reg = epci_base + SCC_EPCI_ABTSET;
304 out_be32(reg, 0x0f1f001f); /* temporary value */
305
306 /* buffer on */
307 reg = epci_base + SCC_EPCI_CLKRST;
308 val = in_be32(reg);
309 val |= SCC_EPCI_CLKRST_BC;
310 out_be32(reg, val);
311
312 /* PCI clock enable */
313 val = in_be32(reg);
314 val |= SCC_EPCI_CLKRST_PCKEN;
315 out_be32(reg, val);
316
317 /* release PCI core reset (all) */
318 reg = epci_base + SCC_EPCI_CKCTRL;
319 val = in_be32(reg);
320 val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
321 out_be32(reg, val);
322
323 /* set base translation registers. (already set by Beat) */
324
325 /* set base address masks. (already set by Beat) */
326 }
327
328 /* release interrupt masks and clear all interrupts */
329 reg = epci_base + SCC_EPCI_INTSET;
330 out_be32(reg, 0x013f011f); /* all interrupts enable */
331 reg = epci_base + SCC_EPCI_VIENAB;
332 val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
333 out_be32(reg, val);
334 reg = epci_base + SCC_EPCI_STATUS;
335 out_be32(reg, 0xffffffff);
336 reg = epci_base + SCC_EPCI_VISTAT;
337 out_be32(reg, 0xffffffff);
338
339 /* disable PCI->IB address translation */
340 reg = epci_base + SCC_EPCI_VCSR;
341 val = in_be32(reg);
342 val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
343 out_be32(reg, val);
344
345 /* set base addresses. (no need to set?) */
346
347 /* memory space, bus master enable */
348 reg = epci_base + PCI_COMMAND;
349 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
350 out_be32(reg, val);
351
352 /* endian mode setup */
353 reg = epci_base + SCC_EPCI_ECMODE;
354 val = 0x00550155;
355 out_be32(reg, val);
356
357 /* set control option */
358 reg = epci_base + SCC_EPCI_CNTOPT;
359 val = in_be32(reg);
360 val |= SCC_EPCI_CNTOPT_O2PMB;
361 out_be32(reg, val);
362
363 /* XXX: temporay: set registers for address conversion setup */
364 reg = epci_base + SCC_EPCI_CNF10_REG;
365 out_be32(reg, 0x80000008);
366 reg = epci_base + SCC_EPCI_CNF14_REG;
367 out_be32(reg, 0x40000008);
368
369 reg = epci_base + SCC_EPCI_BAM0;
370 out_be32(reg, 0x80000000);
371 reg = epci_base + SCC_EPCI_BAM1;
372 out_be32(reg, 0xe0000000);
373
374 reg = epci_base + SCC_EPCI_PVBAT;
375 out_be32(reg, 0x80000000);
376
377 if (!hwres) {
378 /* release external PCI reset */
379 reg = epci_base + SCC_EPCI_CLKRST;
380 val = in_be32(reg);
381 val |= SCC_EPCI_CLKRST_PCIRST;
382 out_be32(reg, val);
383 }
384
385 return 0;
386}
387
388static int __init celleb_setup_epci(struct device_node *node,
389 struct pci_controller *hose)
390{
391 struct resource r;
392
393 pr_debug("PCI: celleb_setup_epci()\n");
394
395 /*
396 * Note:
397 * Celleb epci uses cfg_addr and cfg_data member of
398 * pci_controller structure in irregular way.
399 *
400 * cfg_addr is used to map for control registers of
401 * celleb epci.
402 *
403 * cfg_data is used for configuration area of devices
404 * on Celleb epci buses.
405 */
406
407 if (of_address_to_resource(node, 0, &r))
408 goto error;
409 hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
410 if (!hose->cfg_addr)
411 goto error;
412 pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
413 r.start, (unsigned long)hose->cfg_addr,
414 (r.end - r.start + 1));
415
416 if (of_address_to_resource(node, 2, &r))
417 goto error;
418 hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
419 if (!hose->cfg_data)
420 goto error;
421 pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
422 r.start, (unsigned long)hose->cfg_data,
423 (r.end - r.start + 1));
424
425 hose->ops = &celleb_epci_ops;
426 celleb_epci_init(hose);
427
428 return 0;
429
430error:
431 if (hose->cfg_addr)
432 iounmap(hose->cfg_addr);
433
434 if (hose->cfg_data)
435 iounmap(hose->cfg_data);
436 return 1;
437}
438
439struct celleb_phb_spec celleb_epci_spec __initdata = {
440 .setup = celleb_setup_epci,
441 .ops = &spiderpci_ops,
442 .iowa_init = &spiderpci_iowa_init,
443 .iowa_data = (void *)0,
444};
diff --git a/arch/powerpc/platforms/celleb/scc_sio.c b/arch/powerpc/platforms/celleb/scc_sio.c
deleted file mode 100644
index 3a16c5b3c464..000000000000
--- a/arch/powerpc/platforms/celleb/scc_sio.c
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * setup serial port in SCC
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/tty.h>
22#include <linux/serial.h>
23#include <linux/serial_core.h>
24#include <linux/console.h>
25
26#include <asm/io.h>
27#include <asm/prom.h>
28
29/* sio irq0=0xb00010022 irq0=0xb00010023 irq2=0xb00010024
30 mmio=0xfff000-0x1000,0xff2000-0x1000 */
31static int txx9_serial_bitmap __initdata;
32
33static struct {
34 uint32_t offset;
35 uint32_t index;
36} txx9_scc_tab[3] __initdata = {
37 { 0x300, 0 }, /* 0xFFF300 */
38 { 0x400, 0 }, /* 0xFFF400 */
39 { 0x800, 1 } /* 0xFF2800 */
40};
41
42static int __init txx9_serial_init(void)
43{
44 extern int early_serial_txx9_setup(struct uart_port *port);
45 struct device_node *node = NULL;
46 int i;
47 struct uart_port req;
48 struct of_irq irq;
49 struct resource res;
50
51 while ((node = of_find_compatible_node(node,
52 "serial", "toshiba,sio-scc")) != NULL) {
53 for (i = 0; i < ARRAY_SIZE(txx9_scc_tab); i++) {
54 if (!(txx9_serial_bitmap & (1<<i)))
55 continue;
56
57 if (of_irq_map_one(node, i, &irq))
58 continue;
59 if (of_address_to_resource(node,
60 txx9_scc_tab[i].index, &res))
61 continue;
62
63 memset(&req, 0, sizeof(req));
64 req.line = i;
65 req.iotype = UPIO_MEM;
66 req.mapbase = res.start + txx9_scc_tab[i].offset;
67#ifdef CONFIG_SERIAL_TXX9_CONSOLE
68 req.membase = ioremap(req.mapbase, 0x24);
69#endif
70 req.irq = irq_create_of_mapping(irq.controller,
71 irq.specifier, irq.size);
72 req.flags |= UPF_IOREMAP | UPF_BUGGY_UART
73 /*HAVE_CTS_LINE*/;
74 req.uartclk = 83300000;
75 early_serial_txx9_setup(&req);
76 }
77 }
78
79 return 0;
80}
81
82static int __init txx9_serial_config(char *ptr)
83{
84 int i;
85
86 for (;;) {
87 switch (get_option(&ptr, &i)) {
88 default:
89 return 0;
90 case 2:
91 txx9_serial_bitmap |= 1 << i;
92 break;
93 case 1:
94 txx9_serial_bitmap |= 1 << i;
95 return 0;
96 }
97 }
98}
99__setup("txx9_serial=", txx9_serial_config);
100
101console_initcall(txx9_serial_init);
diff --git a/arch/powerpc/platforms/celleb/scc_uhc.c b/arch/powerpc/platforms/celleb/scc_uhc.c
deleted file mode 100644
index cb4307994087..000000000000
--- a/arch/powerpc/platforms/celleb/scc_uhc.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * SCC (Super Companion Chip) UHC setup
3 *
4 * (C) Copyright 2006-2007 TOSHIBA CORPORATION
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/pci.h>
23
24#include <asm/delay.h>
25#include <asm/io.h>
26#include <asm/machdep.h>
27
28#include "scc.h"
29
30#define UHC_RESET_WAIT_MAX 10000
31
32static inline int uhc_clkctrl_ready(u32 val)
33{
34 const u32 mask = SCC_UHC_USBCEN | SCC_UHC_USBCEN;
35 return((val & mask) == mask);
36}
37
38/*
39 * UHC(usb host controller) enable function.
40 * affect to both of OHCI and EHCI core module.
41 */
42static void enable_scc_uhc(struct pci_dev *dev)
43{
44 void __iomem *uhc_base;
45 u32 __iomem *uhc_clkctrl;
46 u32 __iomem *uhc_ecmode;
47 u32 val = 0;
48 int i;
49
50 if (!machine_is(celleb_beat) &&
51 !machine_is(celleb_native))
52 return;
53
54 uhc_base = ioremap(pci_resource_start(dev, 0),
55 pci_resource_len(dev, 0));
56 if (!uhc_base) {
57 printk(KERN_ERR "failed to map UHC register base.\n");
58 return;
59 }
60 uhc_clkctrl = uhc_base + SCC_UHC_CKRCTRL;
61 uhc_ecmode = uhc_base + SCC_UHC_ECMODE;
62
63 /* setup for normal mode */
64 val |= SCC_UHC_F48MCKLEN;
65 out_be32(uhc_clkctrl, val);
66 val |= SCC_UHC_PHY_SUSPEND_SEL;
67 out_be32(uhc_clkctrl, val);
68 udelay(10);
69 val |= SCC_UHC_PHYEN;
70 out_be32(uhc_clkctrl, val);
71 udelay(50);
72
73 /* disable reset */
74 val |= SCC_UHC_HCLKEN;
75 out_be32(uhc_clkctrl, val);
76 val |= (SCC_UHC_USBCEN | SCC_UHC_USBEN);
77 out_be32(uhc_clkctrl, val);
78 i = 0;
79 while (!uhc_clkctrl_ready(in_be32(uhc_clkctrl))) {
80 udelay(10);
81 if (i++ > UHC_RESET_WAIT_MAX) {
82 printk(KERN_ERR "Failed to disable UHC reset %x\n",
83 in_be32(uhc_clkctrl));
84 break;
85 }
86 }
87
88 /* Endian Conversion Mode for Master ALL area */
89 out_be32(uhc_ecmode, SCC_UHC_ECMODE_BY_BYTE);
90
91 iounmap(uhc_base);
92}
93
94DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
95 PCI_DEVICE_ID_TOSHIBA_SCC_USB, enable_scc_uhc);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 06:24:55 -0500