diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-09-07 02:19:51 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2009-09-07 02:19:51 -0400 |
commit | a1922ed661ab2c1637d0b10cde933bd9cd33d965 (patch) | |
tree | 0f1777542b385ebefd30b3586d830fd8ed6fda5b /arch/powerpc/platforms/cell | |
parent | 75e33751ca8bbb72dd6f1a74d2810ddc8cbe4bdf (diff) | |
parent | d28daf923ac5e4a0d7cecebae56f3e339189366b (diff) |
Merge branch 'tracing/core' into tracing/hw-breakpoints
Conflicts:
arch/Kconfig
kernel/trace/trace.h
Merge reason: resolve the conflicts, plus adopt to the new
ring-buffer APIs.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/powerpc/platforms/cell')
-rw-r--r-- | arch/powerpc/platforms/cell/axon_msi.c | 22 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/smp.c | 30 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/spu_fault.c | 2 |
3 files changed, 14 insertions, 40 deletions
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index c71498dbf211..aca5741ddc67 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c | |||
@@ -85,7 +85,7 @@ static inline void axon_msi_debug_setup(struct device_node *dn, | |||
85 | 85 | ||
86 | static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) | 86 | static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) |
87 | { | 87 | { |
88 | pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); | 88 | pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); |
89 | 89 | ||
90 | dcr_write(msic->dcr_host, dcr_n, val); | 90 | dcr_write(msic->dcr_host, dcr_n, val); |
91 | } | 91 | } |
@@ -98,7 +98,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
98 | int retry = 0; | 98 | int retry = 0; |
99 | 99 | ||
100 | write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); | 100 | write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG); |
101 | pr_debug("axon_msi: original write_offset 0x%x\n", write_offset); | 101 | pr_devel("axon_msi: original write_offset 0x%x\n", write_offset); |
102 | 102 | ||
103 | /* write_offset doesn't wrap properly, so we have to mask it */ | 103 | /* write_offset doesn't wrap properly, so we have to mask it */ |
104 | write_offset &= MSIC_FIFO_SIZE_MASK; | 104 | write_offset &= MSIC_FIFO_SIZE_MASK; |
@@ -108,7 +108,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
108 | msi = le32_to_cpu(msic->fifo_virt[idx]); | 108 | msi = le32_to_cpu(msic->fifo_virt[idx]); |
109 | msi &= 0xFFFF; | 109 | msi &= 0xFFFF; |
110 | 110 | ||
111 | pr_debug("axon_msi: woff %x roff %x msi %x\n", | 111 | pr_devel("axon_msi: woff %x roff %x msi %x\n", |
112 | write_offset, msic->read_offset, msi); | 112 | write_offset, msic->read_offset, msi); |
113 | 113 | ||
114 | if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) { | 114 | if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) { |
@@ -123,12 +123,12 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
123 | */ | 123 | */ |
124 | udelay(1); | 124 | udelay(1); |
125 | retry++; | 125 | retry++; |
126 | pr_debug("axon_msi: invalid irq 0x%x!\n", msi); | 126 | pr_devel("axon_msi: invalid irq 0x%x!\n", msi); |
127 | continue; | 127 | continue; |
128 | } | 128 | } |
129 | 129 | ||
130 | if (retry) { | 130 | if (retry) { |
131 | pr_debug("axon_msi: late irq 0x%x, retry %d\n", | 131 | pr_devel("axon_msi: late irq 0x%x, retry %d\n", |
132 | msi, retry); | 132 | msi, retry); |
133 | retry = 0; | 133 | retry = 0; |
134 | } | 134 | } |
@@ -332,7 +332,7 @@ static int axon_msi_shutdown(struct of_device *device) | |||
332 | struct axon_msic *msic = dev_get_drvdata(&device->dev); | 332 | struct axon_msic *msic = dev_get_drvdata(&device->dev); |
333 | u32 tmp; | 333 | u32 tmp; |
334 | 334 | ||
335 | pr_debug("axon_msi: disabling %s\n", | 335 | pr_devel("axon_msi: disabling %s\n", |
336 | msic->irq_host->of_node->full_name); | 336 | msic->irq_host->of_node->full_name); |
337 | tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); | 337 | tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG); |
338 | tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; | 338 | tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE; |
@@ -349,7 +349,7 @@ static int axon_msi_probe(struct of_device *device, | |||
349 | unsigned int virq; | 349 | unsigned int virq; |
350 | int dcr_base, dcr_len; | 350 | int dcr_base, dcr_len; |
351 | 351 | ||
352 | pr_debug("axon_msi: setting up dn %s\n", dn->full_name); | 352 | pr_devel("axon_msi: setting up dn %s\n", dn->full_name); |
353 | 353 | ||
354 | msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL); | 354 | msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL); |
355 | if (!msic) { | 355 | if (!msic) { |
@@ -403,7 +403,7 @@ static int axon_msi_probe(struct of_device *device, | |||
403 | 403 | ||
404 | set_irq_data(virq, msic); | 404 | set_irq_data(virq, msic); |
405 | set_irq_chained_handler(virq, axon_msi_cascade); | 405 | set_irq_chained_handler(virq, axon_msi_cascade); |
406 | pr_debug("axon_msi: irq 0x%x setup for axon_msi\n", virq); | 406 | pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq); |
407 | 407 | ||
408 | /* Enable the MSIC hardware */ | 408 | /* Enable the MSIC hardware */ |
409 | msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32); | 409 | msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32); |
@@ -484,13 +484,13 @@ void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic) | |||
484 | 484 | ||
485 | addr = of_translate_address(dn, of_get_property(dn, "reg", NULL)); | 485 | addr = of_translate_address(dn, of_get_property(dn, "reg", NULL)); |
486 | if (addr == OF_BAD_ADDR) { | 486 | if (addr == OF_BAD_ADDR) { |
487 | pr_debug("axon_msi: couldn't translate reg property\n"); | 487 | pr_devel("axon_msi: couldn't translate reg property\n"); |
488 | return; | 488 | return; |
489 | } | 489 | } |
490 | 490 | ||
491 | msic->trigger = ioremap(addr, 0x4); | 491 | msic->trigger = ioremap(addr, 0x4); |
492 | if (!msic->trigger) { | 492 | if (!msic->trigger) { |
493 | pr_debug("axon_msi: ioremap failed\n"); | 493 | pr_devel("axon_msi: ioremap failed\n"); |
494 | return; | 494 | return; |
495 | } | 495 | } |
496 | 496 | ||
@@ -498,7 +498,7 @@ void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic) | |||
498 | 498 | ||
499 | if (!debugfs_create_file(name, 0600, powerpc_debugfs_root, | 499 | if (!debugfs_create_file(name, 0600, powerpc_debugfs_root, |
500 | msic, &fops_msic)) { | 500 | msic, &fops_msic)) { |
501 | pr_debug("axon_msi: debugfs_create_file failed!\n"); | 501 | pr_devel("axon_msi: debugfs_create_file failed!\n"); |
502 | return; | 502 | return; |
503 | } | 503 | } |
504 | } | 504 | } |
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c index 9046803c8276..bc97fada48c6 100644 --- a/arch/powerpc/platforms/cell/smp.c +++ b/arch/powerpc/platforms/cell/smp.c | |||
@@ -36,7 +36,6 @@ | |||
36 | #include <asm/prom.h> | 36 | #include <asm/prom.h> |
37 | #include <asm/smp.h> | 37 | #include <asm/smp.h> |
38 | #include <asm/paca.h> | 38 | #include <asm/paca.h> |
39 | #include <asm/time.h> | ||
40 | #include <asm/machdep.h> | 39 | #include <asm/machdep.h> |
41 | #include <asm/cputable.h> | 40 | #include <asm/cputable.h> |
42 | #include <asm/firmware.h> | 41 | #include <asm/firmware.h> |
@@ -140,31 +139,6 @@ static void __devinit smp_cell_setup_cpu(int cpu) | |||
140 | mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); | 139 | mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); |
141 | } | 140 | } |
142 | 141 | ||
143 | static DEFINE_SPINLOCK(timebase_lock); | ||
144 | static unsigned long timebase = 0; | ||
145 | |||
146 | static void __devinit cell_give_timebase(void) | ||
147 | { | ||
148 | spin_lock(&timebase_lock); | ||
149 | rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL); | ||
150 | timebase = get_tb(); | ||
151 | spin_unlock(&timebase_lock); | ||
152 | |||
153 | while (timebase) | ||
154 | barrier(); | ||
155 | rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL); | ||
156 | } | ||
157 | |||
158 | static void __devinit cell_take_timebase(void) | ||
159 | { | ||
160 | while (!timebase) | ||
161 | barrier(); | ||
162 | spin_lock(&timebase_lock); | ||
163 | set_tb(timebase >> 32, timebase & 0xffffffff); | ||
164 | timebase = 0; | ||
165 | spin_unlock(&timebase_lock); | ||
166 | } | ||
167 | |||
168 | static void __devinit smp_cell_kick_cpu(int nr) | 142 | static void __devinit smp_cell_kick_cpu(int nr) |
169 | { | 143 | { |
170 | BUG_ON(nr < 0 || nr >= NR_CPUS); | 144 | BUG_ON(nr < 0 || nr >= NR_CPUS); |
@@ -224,8 +198,8 @@ void __init smp_init_cell(void) | |||
224 | 198 | ||
225 | /* Non-lpar has additional take/give timebase */ | 199 | /* Non-lpar has additional take/give timebase */ |
226 | if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { | 200 | if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) { |
227 | smp_ops->give_timebase = cell_give_timebase; | 201 | smp_ops->give_timebase = rtas_give_timebase; |
228 | smp_ops->take_timebase = cell_take_timebase; | 202 | smp_ops->take_timebase = rtas_take_timebase; |
229 | } | 203 | } |
230 | 204 | ||
231 | DBG(" <- smp_init_cell()\n"); | 205 | DBG(" <- smp_init_cell()\n"); |
diff --git a/arch/powerpc/platforms/cell/spu_fault.c b/arch/powerpc/platforms/cell/spu_fault.c index 95d8dadf2d87..d06ba87f1a19 100644 --- a/arch/powerpc/platforms/cell/spu_fault.c +++ b/arch/powerpc/platforms/cell/spu_fault.c | |||
@@ -70,7 +70,7 @@ int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea, | |||
70 | } | 70 | } |
71 | 71 | ||
72 | ret = 0; | 72 | ret = 0; |
73 | *flt = handle_mm_fault(mm, vma, ea, is_write); | 73 | *flt = handle_mm_fault(mm, vma, ea, is_write ? FAULT_FLAG_WRITE : 0); |
74 | if (unlikely(*flt & VM_FAULT_ERROR)) { | 74 | if (unlikely(*flt & VM_FAULT_ERROR)) { |
75 | if (*flt & VM_FAULT_OOM) { | 75 | if (*flt & VM_FAULT_OOM) { |
76 | ret = -ENOMEM; | 76 | ret = -ENOMEM; |