Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (49 commits)
  powerpc: Fix build bug with binutils < 2.18 and GCC < 4.2
  powerpc/eeh: Don't panic when EEH_MAX_FAILS is exceeded
  fbdev: Teaches offb about palette on radeon r5xx/r6xx
  powerpc/cell/edac: Log a syndrome code in case of correctable error
  powerpc/cell: Add DMA_ATTR_WEAK_ORDERING dma attribute and use in Cell IOMMU code
  powerpc: Indicate which oprofile counters to use while in compat mode
  powerpc/boot: Change spaces to tabs
  powerpc: Remove duplicate 6xx option in Kconfig
  powerpc: Use PPC_LONG and PPC_LONG_ALIGN in lib/string.S
  powerpc: Use PPC_LONG_ALIGN in uaccess.h
  powerpc: Add a #define for aligning to a long-sized boundary
  powerpc: Fix OF parsing of 64 bits PCI addresses
  powerpc: Use WARN_ON(1) instead of __WARN()
  powerpc: Fix support for latencytop
  powerpc/ps3: Update ps3_defconfig
  powerpc/ps3: Add a sub-match id to ps3_system_bus
  powerpc: Add a 6xx defconfig
  powerpc/dma: Use the struct dma_attrs in iommu code
  powerpc/cell: Add support for power button of future IBM cell blades
  powerpc/cell: Cleanup sysreset_hack for IBM cell blades
  ...

8 files changed, 496 insertions, 33 deletions

diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 3959fcfe731c..c14d7d8d96c8 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -83,6 +83,22 @@ config CBE_RAS
         depends on PPC_CELL_NATIVE
         default y
 
+config PPC_IBM_CELL_RESETBUTTON
+        bool "IBM Cell Blade Pinhole reset button"
+        depends on CBE_RAS && PPC_IBM_CELL_BLADE
+        default y
+        help
+          Support Pinhole Resetbutton on IBM Cell blades.
+          This adds a method to trigger system reset via front panel pinhole button.
+
+config PPC_IBM_CELL_POWERBUTTON
+        tristate "IBM Cell Blade power button"
+        depends on PPC_IBM_CELL_BLADE && PPC_PMI && INPUT_EVDEV
+        default y
+        help
+          Support Powerbutton on IBM Cell blades.
+          This will enable the powerbutton as an input device.
+
 config CBE_THERM
         tristate "CBE thermal support"
         default m
@@ -107,6 +123,15 @@ config CBE_CPUFREQ_PMI
           processor will not only be able to run at lower speed,
           but also at lower core voltage.
 
+config CBE_CPUFREQ_SPU_GOVERNOR
+        tristate "CBE frequency scaling based on SPU usage"
+        depends on SPU_FS && CPU_FREQ
+        default m
+        help
+          This governor checks for spu usage to adjust the cpu frequency.
+          If no spu is running on a given cpu, that cpu will be throttled to
+          the minimal possible frequency.
+
 endmenu
 
 config OPROFILE_CELL
diff --git a/arch/powerpc/platforms/cell/Makefile b/arch/powerpc/platforms/cell/Makefile
index c2a7e4e5ddf9..7fd830872c43 100644
--- a/arch/powerpc/platforms/cell/Makefile
+++ b/arch/powerpc/platforms/cell/Makefile
@@ -8,6 +8,9 @@ obj-$(CONFIG_CBE_THERM)			+= cbe_thermal.o
 obj-$(CONFIG_CBE_CPUFREQ_PMI)           += cbe_cpufreq_pmi.o
 obj-$(CONFIG_CBE_CPUFREQ)               += cbe-cpufreq.o
 cbe-cpufreq-y                           += cbe_cpufreq_pervasive.o cbe_cpufreq.o
+obj-$(CONFIG_CBE_CPUFREQ_SPU_GOVERNOR)  += cpufreq_spudemand.o
+
+obj-$(CONFIG_PPC_IBM_CELL_POWERBUTTON)  += cbe_powerbutton.o
 
 ifeq ($(CONFIG_SMP),y)
 obj-$(CONFIG_PPC_CELL_NATIVE)           += smp.o
diff --git a/arch/powerpc/platforms/cell/cbe_powerbutton.c b/arch/powerpc/platforms/cell/cbe_powerbutton.c
new file mode 100644
index 000000000000..dcddaa5fcb66
--- /dev/null
+++ b/arch/powerpc/platforms/cell/cbe_powerbutton.c
@@ -0,0 +1,117 @@
+/*
+ * driver for powerbutton on IBM cell blades
+ *
+ * (C) Copyright IBM Corp. 2005-2008
+ *
+ * Author: Christian Krafft <krafft@de.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <asm/pmi.h>
+#include <asm/prom.h>
+
+static struct input_dev *button_dev;
+static struct platform_device *button_pdev;
+
+static void cbe_powerbutton_handle_pmi(pmi_message_t pmi_msg)
+{
+        BUG_ON(pmi_msg.type != PMI_TYPE_POWER_BUTTON);
+
+        input_report_key(button_dev, KEY_POWER, 1);
+        input_sync(button_dev);
+        input_report_key(button_dev, KEY_POWER, 0);
+        input_sync(button_dev);
+}
+
+static struct pmi_handler cbe_pmi_handler = {
+        .type                   = PMI_TYPE_POWER_BUTTON,
+        .handle_pmi_message     = cbe_powerbutton_handle_pmi,
+};
+
+static int __init cbe_powerbutton_init(void)
+{
+        int ret = 0;
+        struct input_dev *dev;
+
+        if (!machine_is_compatible("IBM,CBPLUS-1.0")) {
+                printk(KERN_ERR "%s: Not a cell blade.\n", __func__);
+                ret = -ENODEV;
+                goto out;
+        }
+
+        dev = input_allocate_device();
+        if (!dev) {
+                ret = -ENOMEM;
+                printk(KERN_ERR "%s: Not enough memory.\n", __func__);
+                goto out;
+        }
+
+        set_bit(EV_KEY, dev->evbit);
+        set_bit(KEY_POWER, dev->keybit);
+
+        dev->name = "Power Button";
+        dev->id.bustype = BUS_HOST;
+
+        /* this makes the button look like an acpi power button
+         * no clue whether anyone relies on that though */
+        dev->id.product = 0x02;
+        dev->phys = "LNXPWRBN/button/input0";
+
+        button_pdev = platform_device_register_simple("power_button", 0, NULL, 0);
+        if (IS_ERR(button_pdev)) {
+                ret = PTR_ERR(button_pdev);
+                goto out_free_input;
+        }
+
+        dev->dev.parent = &button_pdev->dev;
+        ret = input_register_device(dev);
+        if (ret) {
+                printk(KERN_ERR "%s: Failed to register device\n", __func__);
+                goto out_free_pdev;
+        }
+
+        button_dev = dev;
+
+        ret = pmi_register_handler(&cbe_pmi_handler);
+        if (ret) {
+                printk(KERN_ERR "%s: Failed to register with pmi.\n", __func__);
+                goto out_free_pdev;
+        }
+
+        goto out;
+
+out_free_pdev:
+        platform_device_unregister(button_pdev);
+out_free_input:
+        input_free_device(dev);
+out:
+        return ret;
+}
+
+static void __exit cbe_powerbutton_exit(void)
+{
+        pmi_unregister_handler(&cbe_pmi_handler);
+        platform_device_unregister(button_pdev);
+        input_free_device(button_dev);
+}
+
+module_init(cbe_powerbutton_init);
+module_exit(cbe_powerbutton_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>");
diff --git a/arch/powerpc/platforms/cell/cpufreq_spudemand.c b/arch/powerpc/platforms/cell/cpufreq_spudemand.c
new file mode 100644
index 000000000000..a3c6c01bd6db
--- /dev/null
+++ b/arch/powerpc/platforms/cell/cpufreq_spudemand.c
@@ -0,0 +1,184 @@
+/*
+ * spu aware cpufreq governor for the cell processor
+ *
+ * © Copyright IBM Corporation 2006-2008
+ *
+ * Author: Christian Krafft <krafft@de.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/cpufreq.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+#include <asm/atomic.h>
+#include <asm/machdep.h>
+#include <asm/spu.h>
+
+#define POLL_TIME       100000          /* in µs */
+#define EXP             753             /* exp(-1) in fixed-point */
+
+struct spu_gov_info_struct {
+        unsigned long busy_spus;        /* fixed-point */
+        struct cpufreq_policy *policy;
+        struct delayed_work work;
+        unsigned int poll_int;          /* µs */
+};
+static DEFINE_PER_CPU(struct spu_gov_info_struct, spu_gov_info);
+
+static struct workqueue_struct *kspugov_wq;
+
+static int calc_freq(struct spu_gov_info_struct *info)
+{
+        int cpu;
+        int busy_spus;
+
+        cpu = info->policy->cpu;
+        busy_spus = atomic_read(&cbe_spu_info[cpu_to_node(cpu)].busy_spus);
+
+        CALC_LOAD(info->busy_spus, EXP, busy_spus * FIXED_1);
+        pr_debug("cpu %d: busy_spus=%d, info->busy_spus=%ld\n",
+                        cpu, busy_spus, info->busy_spus);
+
+        return info->policy->max * info->busy_spus / FIXED_1;
+}
+
+static void spu_gov_work(struct work_struct *work)
+{
+        struct spu_gov_info_struct *info;
+        int delay;
+        unsigned long target_freq;
+
+        info = container_of(work, struct spu_gov_info_struct, work.work);
+
+        /* after cancel_delayed_work_sync we unset info->policy */
+        BUG_ON(info->policy == NULL);
+
+        target_freq = calc_freq(info);
+        __cpufreq_driver_target(info->policy, target_freq, CPUFREQ_RELATION_H);
+
+        delay = usecs_to_jiffies(info->poll_int);
+        queue_delayed_work_on(info->policy->cpu, kspugov_wq, &info->work, delay);
+}
+
+static void spu_gov_init_work(struct spu_gov_info_struct *info)
+{
+        int delay = usecs_to_jiffies(info->poll_int);
+        INIT_DELAYED_WORK_DEFERRABLE(&info->work, spu_gov_work);
+        queue_delayed_work_on(info->policy->cpu, kspugov_wq, &info->work, delay);
+}
+
+static void spu_gov_cancel_work(struct spu_gov_info_struct *info)
+{
+        cancel_delayed_work_sync(&info->work);
+}
+
+static int spu_gov_govern(struct cpufreq_policy *policy, unsigned int event)
+{
+        unsigned int cpu = policy->cpu;
+        struct spu_gov_info_struct *info, *affected_info;
+        int i;
+        int ret = 0;
+
+        info = &per_cpu(spu_gov_info, cpu);
+
+        switch (event) {
+        case CPUFREQ_GOV_START:
+                if (!cpu_online(cpu)) {
+                        printk(KERN_ERR "cpu %d is not online\n", cpu);
+                        ret = -EINVAL;
+                        break;
+                }
+
+                if (!policy->cur) {
+                        printk(KERN_ERR "no cpu specified in policy\n");
+                        ret = -EINVAL;
+                        break;
+                }
+
+                /* initialize spu_gov_info for all affected cpus */
+                for_each_cpu_mask(i, policy->cpus) {
+                        affected_info = &per_cpu(spu_gov_info, i);
+                        affected_info->policy = policy;
+                }
+
+                info->poll_int = POLL_TIME;
+
+                /* setup timer */
+                spu_gov_init_work(info);
+
+                break;
+
+        case CPUFREQ_GOV_STOP:
+                /* cancel timer */
+                spu_gov_cancel_work(info);
+
+                /* clean spu_gov_info for all affected cpus */
+                for_each_cpu_mask (i, policy->cpus) {
+                        info = &per_cpu(spu_gov_info, i);
+                        info->policy = NULL;
+                }
+
+                break;
+        }
+
+        return ret;
+}
+
+static struct cpufreq_governor spu_governor = {
+        .name = "spudemand",
+        .governor = spu_gov_govern,
+        .owner = THIS_MODULE,
+};
+
+/*
+ * module init and destoy
+ */
+
+static int __init spu_gov_init(void)
+{
+        int ret;
+
+        kspugov_wq = create_workqueue("kspugov");
+        if (!kspugov_wq) {
+                printk(KERN_ERR "creation of kspugov failed\n");
+                ret = -EFAULT;
+                goto out;
+        }
+
+        ret = cpufreq_register_governor(&spu_governor);
+        if (ret) {
+                printk(KERN_ERR "registration of governor failed\n");
+                destroy_workqueue(kspugov_wq);
+                goto out;
+        }
+out:
+        return ret;
+}
+
+static void __exit spu_gov_exit(void)
+{
+        cpufreq_unregister_governor(&spu_governor);
+        destroy_workqueue(kspugov_wq);
+}
+
+
+module_init(spu_gov_init);
+module_exit(spu_gov_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>");
+
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index eeacb3a52ca1..208005ca262c 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -173,7 +173,8 @@ static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte,
 }
 
 static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
-                unsigned long uaddr, enum dma_data_direction direction)
+                unsigned long uaddr, enum dma_data_direction direction,
+                struct dma_attrs *attrs)
 {
         int i;
         unsigned long *io_pte, base_pte;
@@ -198,6 +199,8 @@ static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
         base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW |
                 (window->ioid & IOPTE_IOID_Mask);
 #endif
+        if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)))
+                base_pte &= ~IOPTE_SO_RW;
 
         io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
 
@@ -519,7 +522,7 @@ cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
 
         __set_bit(0, window->table.it_map);
         tce_build_cell(&window->table, window->table.it_offset, 1,
-                       (unsigned long)iommu->pad_page, DMA_TO_DEVICE);
+                       (unsigned long)iommu->pad_page, DMA_TO_DEVICE, NULL);
         window->table.it_hint = window->table.it_blocksize;
 
         return window;
@@ -538,7 +541,9 @@ static struct cbe_iommu *cell_iommu_for_node(int nid)
 static unsigned long cell_dma_direct_offset;
 
 static unsigned long dma_iommu_fixed_base;
-struct dma_mapping_ops dma_iommu_fixed_ops;
+
+/* iommu_fixed_is_weak is set if booted with iommu_fixed=weak */
+static int iommu_fixed_is_weak;
 
 static struct iommu_table *cell_get_iommu_table(struct device *dev)
 {
@@ -562,6 +567,98 @@ static struct iommu_table *cell_get_iommu_table(struct device *dev)
         return &window->table;
 }
 
+/* A coherent allocation implies strong ordering */
+
+static void *dma_fixed_alloc_coherent(struct device *dev, size_t size,
+                                      dma_addr_t *dma_handle, gfp_t flag)
+{
+        if (iommu_fixed_is_weak)
+                return iommu_alloc_coherent(dev, cell_get_iommu_table(dev),
+                                            size, dma_handle,
+                                            device_to_mask(dev), flag,
+                                            dev->archdata.numa_node);
+        else
+                return dma_direct_ops.alloc_coherent(dev, size, dma_handle,
+                                                     flag);
+}
+
+static void dma_fixed_free_coherent(struct device *dev, size_t size,
+                                    void *vaddr, dma_addr_t dma_handle)
+{
+        if (iommu_fixed_is_weak)
+                iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr,
+                                    dma_handle);
+        else
+                dma_direct_ops.free_coherent(dev, size, vaddr, dma_handle);
+}
+
+static dma_addr_t dma_fixed_map_single(struct device *dev, void *ptr,
+                                       size_t size,
+                                       enum dma_data_direction direction,
+                                       struct dma_attrs *attrs)
+{
+        if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
+                return dma_direct_ops.map_single(dev, ptr, size, direction,
+                                                 attrs);
+        else
+                return iommu_map_single(dev, cell_get_iommu_table(dev), ptr,
+                                        size, device_to_mask(dev), direction,
+                                        attrs);
+}
+
+static void dma_fixed_unmap_single(struct device *dev, dma_addr_t dma_addr,
+                                   size_t size,
+                                   enum dma_data_direction direction,
+                                   struct dma_attrs *attrs)
+{
+        if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
+                dma_direct_ops.unmap_single(dev, dma_addr, size, direction,
+                                            attrs);
+        else
+                iommu_unmap_single(cell_get_iommu_table(dev), dma_addr, size,
+                                   direction, attrs);
+}
+
+static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg,
+                           int nents, enum dma_data_direction direction,
+                           struct dma_attrs *attrs)
+{
+        if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
+                return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs);
+        else
+                return iommu_map_sg(dev, cell_get_iommu_table(dev), sg, nents,
+                                    device_to_mask(dev), direction, attrs);
+}
+
+static void dma_fixed_unmap_sg(struct device *dev, struct scatterlist *sg,
+                               int nents, enum dma_data_direction direction,
+                               struct dma_attrs *attrs)
+{
+        if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
+                dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs);
+        else
+                iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents, direction,
+                               attrs);
+}
+
+static int dma_fixed_dma_supported(struct device *dev, u64 mask)
+{
+        return mask == DMA_64BIT_MASK;
+}
+
+static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask);
+
+struct dma_mapping_ops dma_iommu_fixed_ops = {
+        .alloc_coherent = dma_fixed_alloc_coherent,
+        .free_coherent  = dma_fixed_free_coherent,
+        .map_single     = dma_fixed_map_single,
+        .unmap_single   = dma_fixed_unmap_single,
+        .map_sg         = dma_fixed_map_sg,
+        .unmap_sg       = dma_fixed_unmap_sg,
+        .dma_supported  = dma_fixed_dma_supported,
+        .set_dma_mask   = dma_set_mask_and_switch,
+};
+
 static void cell_dma_dev_setup_fixed(struct device *dev);
 
 static void cell_dma_dev_setup(struct device *dev)
@@ -918,9 +1015,16 @@ static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
 
         pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
 
-        base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW
+        base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M
                     | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask);
 
+        if (iommu_fixed_is_weak)
+                pr_info("IOMMU: Using weak ordering for fixed mapping\n");
+        else {
+                pr_info("IOMMU: Using strong ordering for fixed mapping\n");
+                base_pte |= IOPTE_SO_RW;
+        }
+
         for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
                 /* Don't touch the dynamic region */
                 ioaddr = uaddr + fbase;
@@ -1036,9 +1140,6 @@ static int __init cell_iommu_fixed_mapping_init(void)
                 cell_iommu_setup_window(iommu, np, dbase, dsize, 0);
         }
 
-        dma_iommu_fixed_ops = dma_direct_ops;
-        dma_iommu_fixed_ops.set_dma_mask = dma_set_mask_and_switch;
-
         dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch;
         set_pci_dma_ops(&dma_iommu_ops);
 
@@ -1052,6 +1153,9 @@ static int __init setup_iommu_fixed(char *str)
         if (strcmp(str, "off") == 0)
                 iommu_fixed_disabled = 1;
 
+        else if (strcmp(str, "weak") == 0)
+                iommu_fixed_is_weak = 1;
+
         return 1;
 }
 __setup("iommu_fixed=", setup_iommu_fixed);
diff --git a/arch/powerpc/platforms/cell/pervasive.c b/arch/powerpc/platforms/cell/pervasive.c
index 8a3631ce912b..efdacc829576 100644
--- a/arch/powerpc/platforms/cell/pervasive.c
+++ b/arch/powerpc/platforms/cell/pervasive.c
@@ -38,8 +38,6 @@
 
 #include "pervasive.h"
 
-static int sysreset_hack;
-
 static void cbe_power_save(void)
 {
         unsigned long ctrl, thread_switch_control;
@@ -87,9 +85,6 @@ static void cbe_power_save(void)
 
 static int cbe_system_reset_exception(struct pt_regs *regs)
 {
-        int cpu;
-        struct cbe_pmd_regs __iomem *pmd;
-
         switch (regs->msr & SRR1_WAKEMASK) {
         case SRR1_WAKEEE:
                 do_IRQ(regs);
@@ -98,19 +93,7 @@ static int cbe_system_reset_exception(struct pt_regs *regs)
                 timer_interrupt(regs);
                 break;
         case SRR1_WAKEMT:
-                /*
-                 * The BMC can inject user triggered system reset exceptions,
-                 * but cannot set the system reset reason in srr1,
-                 * so check an extra register here.
-                 */
-                if (sysreset_hack && (cpu = smp_processor_id()) == 0) {
-                        pmd = cbe_get_cpu_pmd_regs(cpu);
-                        if (in_be64(&pmd->ras_esc_0) & 0xffff) {
-                                out_be64(&pmd->ras_esc_0, 0);
-                                return 0;
-                        }
-                }
-                break;
+                return cbe_sysreset_hack();
 #ifdef CONFIG_CBE_RAS
         case SRR1_WAKESYSERR:
                 cbe_system_error_exception(regs);
@@ -134,8 +117,6 @@ void __init cbe_pervasive_init(void)
         if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
                 return;
 
-        sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0");
-
         for_each_possible_cpu(cpu) {
                 struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
                 if (!regs)
@@ -144,12 +125,6 @@ void __init cbe_pervasive_init(void)
                  /* Enable Pause(0) control bit */
                 out_be64(&regs->pmcr, in_be64(&regs->pmcr) |
                                             CBE_PMD_PAUSE_ZERO_CONTROL);
-
-                /* Enable JTAG system-reset hack */
-                if (sysreset_hack)
-                        out_be32(&regs->fir_mode_reg,
-                                in_be32(&regs->fir_mode_reg) |
-                                CBE_PMD_FIR_MODE_M8);
         }
 
         ppc_md.power_save = cbe_power_save;
diff --git a/arch/powerpc/platforms/cell/pervasive.h b/arch/powerpc/platforms/cell/pervasive.h
index 7b50947f8044..fd4d7b7092b4 100644
--- a/arch/powerpc/platforms/cell/pervasive.h
+++ b/arch/powerpc/platforms/cell/pervasive.h
@@ -30,4 +30,13 @@ extern void cbe_system_error_exception(struct pt_regs *regs);
 extern void cbe_maintenance_exception(struct pt_regs *regs);
 extern void cbe_thermal_exception(struct pt_regs *regs);
 
+#ifdef CONFIG_PPC_IBM_CELL_RESETBUTTON
+extern int cbe_sysreset_hack(void);
+#else
+static inline int cbe_sysreset_hack(void)
+{
+        return 1;
+}
+#endif /* CONFIG_PPC_IBM_CELL_RESETBUTTON */
+
 #endif
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c
index 505f9b9bdf0c..2a14b052abcd 100644
--- a/arch/powerpc/platforms/cell/ras.c
+++ b/arch/powerpc/platforms/cell/ras.c
@@ -236,6 +236,52 @@ static struct notifier_block cbe_ptcal_reboot_notifier = {
         .notifier_call = cbe_ptcal_notify_reboot
 };
 
+#ifdef CONFIG_PPC_IBM_CELL_RESETBUTTON
+static int sysreset_hack;
+
+static int __init cbe_sysreset_init(void)
+{
+        struct cbe_pmd_regs __iomem *regs;
+
+        sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0");
+        if (!sysreset_hack)
+                return 0;
+
+        regs = cbe_get_cpu_pmd_regs(0);
+        if (!regs)
+                return 0;
+
+        /* Enable JTAG system-reset hack */
+        out_be32(&regs->fir_mode_reg,
+                in_be32(&regs->fir_mode_reg) |
+                CBE_PMD_FIR_MODE_M8);
+
+        return 0;
+}
+device_initcall(cbe_sysreset_init);
+
+int cbe_sysreset_hack(void)
+{
+        struct cbe_pmd_regs __iomem *regs;
+
+        /*
+         * The BMC can inject user triggered system reset exceptions,
+         * but cannot set the system reset reason in srr1,
+         * so check an extra register here.
+         */
+        if (sysreset_hack && (smp_processor_id() == 0)) {
+                regs = cbe_get_cpu_pmd_regs(0);
+                if (!regs)
+                        return 0;
+                if (in_be64(&regs->ras_esc_0) & 0x0000ffff) {
+                        out_be64(&regs->ras_esc_0, 0);
+                        return 0;
+                }
+        }
+        return 1;
+}
+#endif /* CONFIG_PPC_IBM_CELL_RESETBUTTON */
+
 int __init cbe_ptcal_init(void)
 {
         int ret;