diff options
author | Christian Krafft <krafft@de.ibm.com> | 2008-07-15 15:51:44 -0400 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2008-07-21 20:39:31 -0400 |
commit | 70694a8bab22bd0cc98ff4ee5cc75fe9be30fcd0 (patch) | |
tree | 9dab5e6d7d17deda385f21cafb7035857d1db38c /arch/powerpc/platforms/cell | |
parent | 880e710580c09bf86cddac687fc492a8318934fe (diff) |
powerpc/cell: Cleanup sysreset_hack for IBM cell blades
This patch adds a config option for the sysreset_hack used for
IBM Cell blades. The code is moves from pervasive.c into ras.c and
gets it's own init method.
Signed-off-by: Christian Krafft <krafft@de.ibm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/platforms/cell')
-rw-r--r-- | arch/powerpc/platforms/cell/Kconfig | 8 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/pervasive.c | 27 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/pervasive.h | 9 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/ras.c | 46 |
4 files changed, 64 insertions, 26 deletions
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig index 6ee571f743c5..2d1957bc450d 100644 --- a/arch/powerpc/platforms/cell/Kconfig +++ b/arch/powerpc/platforms/cell/Kconfig | |||
@@ -83,6 +83,14 @@ config CBE_RAS | |||
83 | depends on PPC_CELL_NATIVE | 83 | depends on PPC_CELL_NATIVE |
84 | default y | 84 | default y |
85 | 85 | ||
86 | config PPC_IBM_CELL_RESETBUTTON | ||
87 | bool "IBM Cell Blade Pinhole reset button" | ||
88 | depends on CBE_RAS && PPC_IBM_CELL_BLADE | ||
89 | default y | ||
90 | help | ||
91 | Support Pinhole Resetbutton on IBM Cell blades. | ||
92 | This adds a method to trigger system reset via front panel pinhole button. | ||
93 | |||
86 | config CBE_THERM | 94 | config CBE_THERM |
87 | tristate "CBE thermal support" | 95 | tristate "CBE thermal support" |
88 | default m | 96 | default m |
diff --git a/arch/powerpc/platforms/cell/pervasive.c b/arch/powerpc/platforms/cell/pervasive.c index 8a3631ce912b..efdacc829576 100644 --- a/arch/powerpc/platforms/cell/pervasive.c +++ b/arch/powerpc/platforms/cell/pervasive.c | |||
@@ -38,8 +38,6 @@ | |||
38 | 38 | ||
39 | #include "pervasive.h" | 39 | #include "pervasive.h" |
40 | 40 | ||
41 | static int sysreset_hack; | ||
42 | |||
43 | static void cbe_power_save(void) | 41 | static void cbe_power_save(void) |
44 | { | 42 | { |
45 | unsigned long ctrl, thread_switch_control; | 43 | unsigned long ctrl, thread_switch_control; |
@@ -87,9 +85,6 @@ static void cbe_power_save(void) | |||
87 | 85 | ||
88 | static int cbe_system_reset_exception(struct pt_regs *regs) | 86 | static int cbe_system_reset_exception(struct pt_regs *regs) |
89 | { | 87 | { |
90 | int cpu; | ||
91 | struct cbe_pmd_regs __iomem *pmd; | ||
92 | |||
93 | switch (regs->msr & SRR1_WAKEMASK) { | 88 | switch (regs->msr & SRR1_WAKEMASK) { |
94 | case SRR1_WAKEEE: | 89 | case SRR1_WAKEEE: |
95 | do_IRQ(regs); | 90 | do_IRQ(regs); |
@@ -98,19 +93,7 @@ static int cbe_system_reset_exception(struct pt_regs *regs) | |||
98 | timer_interrupt(regs); | 93 | timer_interrupt(regs); |
99 | break; | 94 | break; |
100 | case SRR1_WAKEMT: | 95 | case SRR1_WAKEMT: |
101 | /* | 96 | return cbe_sysreset_hack(); |
102 | * The BMC can inject user triggered system reset exceptions, | ||
103 | * but cannot set the system reset reason in srr1, | ||
104 | * so check an extra register here. | ||
105 | */ | ||
106 | if (sysreset_hack && (cpu = smp_processor_id()) == 0) { | ||
107 | pmd = cbe_get_cpu_pmd_regs(cpu); | ||
108 | if (in_be64(&pmd->ras_esc_0) & 0xffff) { | ||
109 | out_be64(&pmd->ras_esc_0, 0); | ||
110 | return 0; | ||
111 | } | ||
112 | } | ||
113 | break; | ||
114 | #ifdef CONFIG_CBE_RAS | 97 | #ifdef CONFIG_CBE_RAS |
115 | case SRR1_WAKESYSERR: | 98 | case SRR1_WAKESYSERR: |
116 | cbe_system_error_exception(regs); | 99 | cbe_system_error_exception(regs); |
@@ -134,8 +117,6 @@ void __init cbe_pervasive_init(void) | |||
134 | if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO)) | 117 | if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO)) |
135 | return; | 118 | return; |
136 | 119 | ||
137 | sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0"); | ||
138 | |||
139 | for_each_possible_cpu(cpu) { | 120 | for_each_possible_cpu(cpu) { |
140 | struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu); | 121 | struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu); |
141 | if (!regs) | 122 | if (!regs) |
@@ -144,12 +125,6 @@ void __init cbe_pervasive_init(void) | |||
144 | /* Enable Pause(0) control bit */ | 125 | /* Enable Pause(0) control bit */ |
145 | out_be64(®s->pmcr, in_be64(®s->pmcr) | | 126 | out_be64(®s->pmcr, in_be64(®s->pmcr) | |
146 | CBE_PMD_PAUSE_ZERO_CONTROL); | 127 | CBE_PMD_PAUSE_ZERO_CONTROL); |
147 | |||
148 | /* Enable JTAG system-reset hack */ | ||
149 | if (sysreset_hack) | ||
150 | out_be32(®s->fir_mode_reg, | ||
151 | in_be32(®s->fir_mode_reg) | | ||
152 | CBE_PMD_FIR_MODE_M8); | ||
153 | } | 128 | } |
154 | 129 | ||
155 | ppc_md.power_save = cbe_power_save; | 130 | ppc_md.power_save = cbe_power_save; |
diff --git a/arch/powerpc/platforms/cell/pervasive.h b/arch/powerpc/platforms/cell/pervasive.h index 7b50947f8044..fd4d7b7092b4 100644 --- a/arch/powerpc/platforms/cell/pervasive.h +++ b/arch/powerpc/platforms/cell/pervasive.h | |||
@@ -30,4 +30,13 @@ extern void cbe_system_error_exception(struct pt_regs *regs); | |||
30 | extern void cbe_maintenance_exception(struct pt_regs *regs); | 30 | extern void cbe_maintenance_exception(struct pt_regs *regs); |
31 | extern void cbe_thermal_exception(struct pt_regs *regs); | 31 | extern void cbe_thermal_exception(struct pt_regs *regs); |
32 | 32 | ||
33 | #ifdef CONFIG_PPC_IBM_CELL_RESETBUTTON | ||
34 | extern int cbe_sysreset_hack(void); | ||
35 | #else | ||
36 | static inline int cbe_sysreset_hack(void) | ||
37 | { | ||
38 | return 1; | ||
39 | } | ||
40 | #endif /* CONFIG_PPC_IBM_CELL_RESETBUTTON */ | ||
41 | |||
33 | #endif | 42 | #endif |
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c index 505f9b9bdf0c..2a14b052abcd 100644 --- a/arch/powerpc/platforms/cell/ras.c +++ b/arch/powerpc/platforms/cell/ras.c | |||
@@ -236,6 +236,52 @@ static struct notifier_block cbe_ptcal_reboot_notifier = { | |||
236 | .notifier_call = cbe_ptcal_notify_reboot | 236 | .notifier_call = cbe_ptcal_notify_reboot |
237 | }; | 237 | }; |
238 | 238 | ||
239 | #ifdef CONFIG_PPC_IBM_CELL_RESETBUTTON | ||
240 | static int sysreset_hack; | ||
241 | |||
242 | static int __init cbe_sysreset_init(void) | ||
243 | { | ||
244 | struct cbe_pmd_regs __iomem *regs; | ||
245 | |||
246 | sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0"); | ||
247 | if (!sysreset_hack) | ||
248 | return 0; | ||
249 | |||
250 | regs = cbe_get_cpu_pmd_regs(0); | ||
251 | if (!regs) | ||
252 | return 0; | ||
253 | |||
254 | /* Enable JTAG system-reset hack */ | ||
255 | out_be32(®s->fir_mode_reg, | ||
256 | in_be32(®s->fir_mode_reg) | | ||
257 | CBE_PMD_FIR_MODE_M8); | ||
258 | |||
259 | return 0; | ||
260 | } | ||
261 | device_initcall(cbe_sysreset_init); | ||
262 | |||
263 | int cbe_sysreset_hack(void) | ||
264 | { | ||
265 | struct cbe_pmd_regs __iomem *regs; | ||
266 | |||
267 | /* | ||
268 | * The BMC can inject user triggered system reset exceptions, | ||
269 | * but cannot set the system reset reason in srr1, | ||
270 | * so check an extra register here. | ||
271 | */ | ||
272 | if (sysreset_hack && (smp_processor_id() == 0)) { | ||
273 | regs = cbe_get_cpu_pmd_regs(0); | ||
274 | if (!regs) | ||
275 | return 0; | ||
276 | if (in_be64(®s->ras_esc_0) & 0x0000ffff) { | ||
277 | out_be64(®s->ras_esc_0, 0); | ||
278 | return 0; | ||
279 | } | ||
280 | } | ||
281 | return 1; | ||
282 | } | ||
283 | #endif /* CONFIG_PPC_IBM_CELL_RESETBUTTON */ | ||
284 | |||
239 | int __init cbe_ptcal_init(void) | 285 | int __init cbe_ptcal_init(void) |
240 | { | 286 | { |
241 | int ret; | 287 | int ret; |