[POWERPC] cell: add RAS support

This is a first version of support for the Cell BE "Reliability,
Availability and Serviceability" features.

It doesn't yet handle some of the RAS interrupts (the ones described in
iic_is/iic_irr), I'm still working on a proper way to expose these. They
are essentially a cascaded controller by themselves (sic !) though I may
just handle them locally to the iic driver. I need also to sync with
David Erb on the way he hooked in the performance monitor interrupt.

So that's all for 2.6.17 and I'll do more work on that with my rework of
the powerpc interrupt layer that I'm hacking on at the moment.

Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 4 insertions, 33 deletions

diff --git a/arch/powerpc/platforms/cell/pervasive.h b/arch/powerpc/platforms/cell/pervasive.h
index da1fb85ca3e8..7b50947f8044 100644
--- a/arch/powerpc/platforms/cell/pervasive.h
+++ b/arch/powerpc/platforms/cell/pervasive.h
@@ -25,38 +25,9 @@
 #ifndef PERVASIVE_H
 #define PERVASIVE_H
 
-struct pmd_regs {
-        u8 pad_0x0000_0x0800[0x0800 - 0x0000];                  /* 0x0000 */
-
-        /* Thermal Sensor Registers */
-        u64  ts_ctsr1;                                          /* 0x0800 */
-        u64  ts_ctsr2;                                          /* 0x0808 */
-        u64  ts_mtsr1;                                          /* 0x0810 */
-        u64  ts_mtsr2;                                          /* 0x0818 */
-        u64  ts_itr1;                                           /* 0x0820 */
-        u64  ts_itr2;                                           /* 0x0828 */
-        u64  ts_gitr;                                           /* 0x0830 */
-        u64  ts_isr;                                            /* 0x0838 */
-        u64  ts_imr;                                            /* 0x0840 */
-        u64  tm_cr1;                                            /* 0x0848 */
-        u64  tm_cr2;                                            /* 0x0850 */
-        u64  tm_simr;                                           /* 0x0858 */
-        u64  tm_tpr;                                            /* 0x0860 */
-        u64  tm_str1;                                           /* 0x0868 */
-        u64  tm_str2;                                           /* 0x0870 */
-        u64  tm_tsr;                                            /* 0x0878 */
-
-        /* Power Management */
-        u64  pm_control;                                        /* 0x0880 */
-#define PMD_PAUSE_ZERO_CONTROL          0x10000
-        u64  pm_status;                                         /* 0x0888 */
-
-        /* Time Base Register */
-        u64  tbr;                                               /* 0x0890 */
-
-        u8   pad_0x0898_0x1000 [0x1000 - 0x0898];               /* 0x0898 */
-};
-
-void __init cell_pervasive_init(void);
+extern void cbe_pervasive_init(void);
+extern void cbe_system_error_exception(struct pt_regs *regs);
+extern void cbe_maintenance_exception(struct pt_regs *regs);
+extern void cbe_thermal_exception(struct pt_regs *regs);
 
 #endif