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authorArnd Bergmann <arnd.bergmann@de.ibm.com>2006-03-24 13:47:52 -0500
committerPaul Mackerras <paulus@samba.org>2006-03-26 22:48:42 -0500
commit47952d5ea67dc7098667a954483a82acf81eb4da (patch)
tree1696c80c6b883496006abd0a4586b02a981a50d4 /arch/powerpc/platforms/cell/pervasive.c
parent2fa68747dad290f4415e2ea8565d57876747b2d3 (diff)
[PATCH] powerpc: use guarded ioremap for cell on-chip mappings
I'm not sure where the information came from, but I assumed that doing cache-inhibited mappings for mmio regions was sufficient. It seems we also need the guarded bit set, like everyone else, which is the default for ioremap. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/cell/pervasive.c')
-rw-r--r--arch/powerpc/platforms/cell/pervasive.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/cell/pervasive.c b/arch/powerpc/platforms/cell/pervasive.c
index e0e051c675dd..58baeb52f6fc 100644
--- a/arch/powerpc/platforms/cell/pervasive.c
+++ b/arch/powerpc/platforms/cell/pervasive.c
@@ -203,7 +203,7 @@ found:
203 203
204 pr_debug("pervasive area for CPU %d at %lx, size %x\n", 204 pr_debug("pervasive area for CPU %d at %lx, size %x\n",
205 cpu, real_address, size); 205 cpu, real_address, size);
206 p->regs = __ioremap(real_address, size, _PAGE_NO_CACHE); 206 p->regs = ioremap(real_address, size);
207 p->thread = thread; 207 p->thread = thread;
208 return 0; 208 return 0;
209} 209}