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authorJon Loeliger <jdl@jdl.com>2006-06-17 18:52:48 -0400
committerPaul Mackerras <paulus@samba.org>2006-06-21 01:01:28 -0400
commitb809b3e86f39651475b30ceb1caf535071534d4d (patch)
tree712cc40ccca8871df5c113142880e73a9828dcc9 /arch/powerpc/platforms/86xx
parent4ca4b6274c30d53d22014fb6974efe2b3e52cfdc (diff)
[POWERPC] Add mpc8641hpcn PCI/PCI-Express platform files.
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/86xx')
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_pcie.c173
-rw-r--r--arch/powerpc/platforms/86xx/pci.c325
2 files changed, 498 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_pcie.c b/arch/powerpc/platforms/86xx/mpc86xx_pcie.c
new file mode 100644
index 000000000000..a2f4f730213e
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_pcie.c
@@ -0,0 +1,173 @@
1/*
2 * Support for indirect PCI bridges.
3 *
4 * Copyright (C) 1998 Gabriel Paubert.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * "Temporary" MPC8548 Errata file -
12 * The standard indirect_pci code should work with future silicon versions.
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/string.h>
19#include <linux/init.h>
20#include <linux/bootmem.h>
21
22#include <asm/io.h>
23#include <asm/prom.h>
24#include <asm/pci-bridge.h>
25#include <asm/machdep.h>
26
27#include "mpc86xx.h"
28
29#define PCI_CFG_OUT out_be32
30
31/* ERRATA PCI-Ex 14 PCIE Controller timeout */
32#define PCIE_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
33
34
35static int
36indirect_read_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
37 int len, u32 *val)
38{
39 struct pci_controller *hose = bus->sysdata;
40 volatile void __iomem *cfg_data;
41 u32 temp;
42
43 if (ppc_md.pci_exclude_device)
44 if (ppc_md.pci_exclude_device(bus->number, devfn))
45 return PCIBIOS_DEVICE_NOT_FOUND;
46
47 /* Possible artifact of CDCpp50937 needs further investigation */
48 if (devfn != 0x0 && bus->number == 0xff)
49 return PCIBIOS_DEVICE_NOT_FOUND;
50
51 PCIE_FIX;
52 if (bus->number == 0xff) {
53 PCI_CFG_OUT(hose->cfg_addr,
54 (0x80000000 | ((offset & 0xf00) << 16) |
55 ((bus->number - hose->bus_offset) << 16)
56 | (devfn << 8) | ((offset & 0xfc) )));
57 } else {
58 PCI_CFG_OUT(hose->cfg_addr,
59 (0x80000001 | ((offset & 0xf00) << 16) |
60 ((bus->number - hose->bus_offset) << 16)
61 | (devfn << 8) | ((offset & 0xfc) )));
62 }
63
64 /*
65 * Note: the caller has already checked that offset is
66 * suitably aligned and that len is 1, 2 or 4.
67 */
68 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
69 cfg_data = hose->cfg_data;
70 PCIE_FIX;
71 temp = in_le32(cfg_data);
72 switch (len) {
73 case 1:
74 *val = (temp >> (((offset & 3))*8)) & 0xff;
75 break;
76 case 2:
77 *val = (temp >> (((offset & 3))*8)) & 0xffff;
78 break;
79 default:
80 *val = temp;
81 break;
82 }
83 return PCIBIOS_SUCCESSFUL;
84}
85
86static int
87indirect_write_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
88 int len, u32 val)
89{
90 struct pci_controller *hose = bus->sysdata;
91 volatile void __iomem *cfg_data;
92 u32 temp;
93
94 if (ppc_md.pci_exclude_device)
95 if (ppc_md.pci_exclude_device(bus->number, devfn))
96 return PCIBIOS_DEVICE_NOT_FOUND;
97
98 /* Possible artifact of CDCpp50937 needs further investigation */
99 if (devfn != 0x0 && bus->number == 0xff)
100 return PCIBIOS_DEVICE_NOT_FOUND;
101
102 PCIE_FIX;
103 if (bus->number == 0xff) {
104 PCI_CFG_OUT(hose->cfg_addr,
105 (0x80000000 | ((offset & 0xf00) << 16) |
106 ((bus->number - hose->bus_offset) << 16)
107 | (devfn << 8) | ((offset & 0xfc) )));
108 } else {
109 PCI_CFG_OUT(hose->cfg_addr,
110 (0x80000001 | ((offset & 0xf00) << 16) |
111 ((bus->number - hose->bus_offset) << 16)
112 | (devfn << 8) | ((offset & 0xfc) )));
113 }
114
115 /*
116 * Note: the caller has already checked that offset is
117 * suitably aligned and that len is 1, 2 or 4.
118 */
119 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
120 cfg_data = hose->cfg_data;
121 switch (len) {
122 case 1:
123 PCIE_FIX;
124 temp = in_le32(cfg_data);
125 temp = (temp & ~(0xff << ((offset & 3) * 8))) |
126 (val << ((offset & 3) * 8));
127 PCIE_FIX;
128 out_le32(cfg_data, temp);
129 break;
130 case 2:
131 PCIE_FIX;
132 temp = in_le32(cfg_data);
133 temp = (temp & ~(0xffff << ((offset & 3) * 8)));
134 temp |= (val << ((offset & 3) * 8)) ;
135 PCIE_FIX;
136 out_le32(cfg_data, temp);
137 break;
138 default:
139 PCIE_FIX;
140 out_le32(cfg_data, val);
141 break;
142 }
143 PCIE_FIX;
144 return PCIBIOS_SUCCESSFUL;
145}
146
147static struct pci_ops indirect_pcie_ops = {
148 indirect_read_config_pcie,
149 indirect_write_config_pcie
150};
151
152void __init
153setup_indirect_pcie_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
154 void __iomem * cfg_data)
155{
156 hose->cfg_addr = cfg_addr;
157 hose->cfg_data = cfg_data;
158 hose->ops = &indirect_pcie_ops;
159}
160
161void __init
162setup_indirect_pcie(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
163{
164 unsigned long base = cfg_addr & PAGE_MASK;
165 void __iomem *mbase, *addr, *data;
166
167 mbase = ioremap(base, PAGE_SIZE);
168 addr = mbase + (cfg_addr & ~PAGE_MASK);
169 if ((cfg_data & PAGE_MASK) != base)
170 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
171 data = mbase + (cfg_data & ~PAGE_MASK);
172 setup_indirect_pcie_nomap(hose, addr, data);
173}
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
new file mode 100644
index 000000000000..5180df7c75bc
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -0,0 +1,325 @@
1/*
2 * MPC86XX pci setup code
3 *
4 * Recode: ZHANG WEI <wei.zhang@freescale.com>
5 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
6 *
7 * Copyright 2006 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/config.h>
16#include <linux/types.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/serial.h>
21
22#include <asm/system.h>
23#include <asm/atomic.h>
24#include <asm/io.h>
25#include <asm/prom.h>
26#include <asm/immap_86xx.h>
27#include <asm/pci-bridge.h>
28#include <sysdev/fsl_soc.h>
29
30#include "mpc86xx.h"
31
32#undef DEBUG
33
34#ifdef DEBUG
35#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
36#else
37#define DBG(fmt, args...)
38#endif
39
40struct pcie_outbound_window_regs {
41 uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
42 uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
43 uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
44 char res1[4];
45 uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
46 char res2[12];
47};
48
49struct pcie_inbound_window_regs {
50 uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
51 char res1[4];
52 uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
53 uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
54 uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
55 char res2[12];
56};
57
58static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
59{
60 volatile struct ccsr_pex *pcie;
61 volatile struct pcie_outbound_window_regs *pcieow;
62 volatile struct pcie_inbound_window_regs *pcieiw;
63 int i = 0;
64
65 DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
66 rsrc->end - rsrc->start + 1);
67 pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
68
69 /* Disable all windows (except pexowar0 since its ignored) */
70 pcie->pexowar1 = 0;
71 pcie->pexowar2 = 0;
72 pcie->pexowar3 = 0;
73 pcie->pexowar4 = 0;
74 pcie->pexiwar1 = 0;
75 pcie->pexiwar2 = 0;
76 pcie->pexiwar3 = 0;
77
78 pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
79 pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
80
81 /* Setup outbound MEM window */
82 for(i = 0; i < 3; i++)
83 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
84 DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
85 hose->mem_resources[i].start,
86 hose->mem_resources[i].end
87 - hose->mem_resources[i].start + 1);
88 pcieow->pexotar = (hose->mem_resources[i].start) >> 12
89 & 0x000fffff;
90 pcieow->pexotear = 0;
91 pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
92 & 0x000fffff;
93 /* Enable, Mem R/W */
94 pcieow->pexowar = 0x80044000 |
95 (__ilog2(hose->mem_resources[i].end
96 - hose->mem_resources[i].start + 1)
97 - 1);
98 pcieow++;
99 }
100
101 /* Setup outbound IO window */
102 if (hose->io_resource.flags & IORESOURCE_IO){
103 DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
104 hose->io_resource.start,
105 hose->io_resource.end - hose->io_resource.start + 1,
106 hose->io_base_phys);
107 pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
108 pcieow->pexotear = 0;
109 pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
110 /* Enable, IO R/W */
111 pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
112 - hose->io_resource.start + 1) - 1);
113 }
114
115 /* Setup 2G inbound Memory Window @ 0 */
116 pcieiw->pexitar = 0x00000000;
117 pcieiw->pexiwbar = 0x00000000;
118 /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
119 pcieiw->pexiwar = 0xa0f5501e;
120}
121
122static void __init
123mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
124{
125 volatile struct ccsr_pex *pcie;
126 u16 cmd;
127 unsigned int temps;
128
129 DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
130 pcie_offset, pcie_size);
131
132 pcie = ioremap(pcie_offset, pcie_size);
133
134 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
135 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
136 | PCI_COMMAND_IO;
137 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
138
139 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
140
141 /* PCIE Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */
142 early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &temps);
143 temps = (temps & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
144 early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
145}
146
147int __init add_bridge(struct device_node *dev)
148{
149 int len;
150 struct pci_controller *hose;
151 struct resource rsrc;
152 int *bus_range;
153 int has_address = 0;
154 int primary = 0;
155
156 DBG("Adding PCIE host bridge %s\n", dev->full_name);
157
158 /* Fetch host bridge registers address */
159 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
160
161 /* Get bus range if any */
162 bus_range = (int *) get_property(dev, "bus-range", &len);
163 if (bus_range == NULL || len < 2 * sizeof(int))
164 printk(KERN_WARNING "Can't get bus-range for %s, assume"
165 " bus 0\n", dev->full_name);
166
167 hose = pcibios_alloc_controller();
168 if (!hose)
169 return -ENOMEM;
170 hose->arch_data = dev;
171 hose->set_cfg_type = 1;
172
173 /* last_busno = 0xfe cause by MPC8641 PCIE bug */
174 hose->first_busno = bus_range ? bus_range[0] : 0x0;
175 hose->last_busno = bus_range ? bus_range[1] : 0xfe;
176
177 setup_indirect_pcie(hose, rsrc.start, rsrc.start + 0x4);
178
179 /* Setup the PCIE host controller. */
180 mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
181
182 if ((rsrc.start & 0xfffff) == 0x8000)
183 primary = 1;
184
185 printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
186 "Firmware bus number: %d->%d\n",
187 rsrc.start, hose->first_busno, hose->last_busno);
188
189 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
190 hose, hose->cfg_addr, hose->cfg_data);
191
192 /* Interpret the "ranges" property */
193 /* This also maps the I/O region and sets isa_io/mem_base */
194 pci_process_bridge_OF_ranges(hose, dev, primary);
195
196 /* Setup PEX window registers */
197 setup_pcie_atmu(hose, &rsrc);
198
199 return 0;
200}
201
202static void __devinit quirk_ali1575(struct pci_dev *dev)
203{
204 unsigned short temp;
205
206 /*
207 * ALI1575 interrupts route table setup:
208 *
209 * IRQ pin IRQ#
210 * PIRQA ---- 3
211 * PIRQB ---- 4
212 * PIRQC ---- 5
213 * PIRQD ---- 6
214 * PIRQE ---- 9
215 * PIRQF ---- 10
216 * PIRQG ---- 11
217 * PIRQH ---- 12
218 *
219 * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
220 * PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
221 */
222 pci_write_config_dword(dev, 0x48, 0xb9317542);
223
224 /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
225 pci_write_config_byte(dev, 0x86, 0x0c);
226
227 /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
228 pci_write_config_byte(dev, 0x87, 0x0d);
229
230 /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
231 pci_write_config_byte(dev, 0x88, 0x0f);
232
233 /* USB 2.0 controller, interrupt: PIRQ7 */
234 pci_write_config_byte(dev, 0x74, 0x06);
235
236 /* Audio controller, interrupt: PIRQE */
237 pci_write_config_byte(dev, 0x8a, 0x0c);
238
239 /* Modem controller, interrupt: PIRQF */
240 pci_write_config_byte(dev, 0x8b, 0x0d);
241
242 /* HD audio controller, interrupt: PIRQG */
243 pci_write_config_byte(dev, 0x8c, 0x0e);
244
245 /* Serial ATA interrupt: PIRQD */
246 pci_write_config_byte(dev, 0x8d, 0x0b);
247
248 /* SMB interrupt: PIRQH */
249 pci_write_config_byte(dev, 0x8e, 0x0f);
250
251 /* PMU ACPI SCI interrupt: PIRQH */
252 pci_write_config_byte(dev, 0x8f, 0x0f);
253
254 /* Primary PATA IDE IRQ: 14
255 * Secondary PATA IDE IRQ: 15
256 */
257 pci_write_config_byte(dev, 0x44, 0x3d);
258 pci_write_config_byte(dev, 0x75, 0x0f);
259
260 /* Set IRQ14 and IRQ15 to legacy IRQs */
261 pci_read_config_word(dev, 0x46, &temp);
262 temp |= 0xc000;
263 pci_write_config_word(dev, 0x46, temp);
264
265 /* Set i8259 interrupt trigger
266 * IRQ 3: Level
267 * IRQ 4: Level
268 * IRQ 5: Level
269 * IRQ 6: Level
270 * IRQ 7: Level
271 * IRQ 9: Level
272 * IRQ 10: Level
273 * IRQ 11: Level
274 * IRQ 12: Level
275 * IRQ 14: Edge
276 * IRQ 15: Edge
277 */
278 outb(0xfa, 0x4d0);
279 outb(0x1e, 0x4d1);
280}
281
282static void __devinit quirk_uli5288(struct pci_dev *dev)
283{
284 unsigned char c;
285
286 pci_read_config_byte(dev,0x83,&c);
287 c |= 0x80;
288 pci_write_config_byte(dev, 0x83, c);
289
290 pci_write_config_byte(dev, 0x09, 0x01);
291 pci_write_config_byte(dev, 0x0a, 0x06);
292
293 pci_read_config_byte(dev,0x83,&c);
294 c &= 0x7f;
295 pci_write_config_byte(dev, 0x83, c);
296
297 pci_read_config_byte(dev,0x84,&c);
298 c |= 0x01;
299 pci_write_config_byte(dev, 0x84, c);
300}
301
302static void __devinit quirk_uli5229(struct pci_dev *dev)
303{
304 unsigned short temp;
305 pci_write_config_word(dev, 0x04, 0x0405);
306 pci_read_config_word(dev, 0x4a, &temp);
307 temp |= 0x1000;
308 pci_write_config_word(dev, 0x4a, temp);
309}
310
311static void __devinit early_uli5249(struct pci_dev *dev)
312{
313 unsigned char temp;
314 pci_write_config_word(dev, 0x04, 0x0007);
315 pci_read_config_byte(dev, 0x7c, &temp);
316 pci_write_config_byte(dev, 0x7c, 0x80);
317 pci_write_config_byte(dev, 0x09, 0x01);
318 pci_write_config_byte(dev, 0x7c, temp);
319 dev->class |= 0x1;
320}
321
322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
325DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 04:03:32 -0500