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authorJon Loeliger <jdl@freescale.com>2007-03-07 15:48:45 -0500
committerKumar Gala <galak@kernel.crashing.org>2007-03-26 18:03:25 -0400
commit3e4e97f42e134e1fe46bdf36bd5d874f5b4f8755 (patch)
tree21b019e1c7258a408bec7059ddfee939f2b8e7f1 /arch/powerpc/platforms/86xx
parente0e3c8d432ab9503b167e53d60b145f0e26bb1e2 (diff)
[POWERPC] 86xx/85xx: Move 8641 PCI-Express to arch/powerpc/sysdev/fsl_pcie.c.
This move sets the stage for the use of generic PCI Express code in 85xx and 86xx parts from FSL. Subsequent patches for 8548 and 8544 will be able to use this shared code. Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/platforms/86xx')
-rw-r--r--arch/powerpc/platforms/86xx/Makefile2
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_pcie.c173
2 files changed, 1 insertions, 174 deletions
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 476a6eeee710..418fd8f4d268 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -4,4 +4,4 @@
4 4
5obj-$(CONFIG_SMP) += mpc86xx_smp.o 5obj-$(CONFIG_SMP) += mpc86xx_smp.o
6obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o 6obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
7obj-$(CONFIG_PCI) += pci.o mpc86xx_pcie.o 7obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_pcie.c b/arch/powerpc/platforms/86xx/mpc86xx_pcie.c
deleted file mode 100644
index a2f4f730213e..000000000000
--- a/arch/powerpc/platforms/86xx/mpc86xx_pcie.c
+++ /dev/null
@@ -1,173 +0,0 @@
1/*
2 * Support for indirect PCI bridges.
3 *
4 * Copyright (C) 1998 Gabriel Paubert.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * "Temporary" MPC8548 Errata file -
12 * The standard indirect_pci code should work with future silicon versions.
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/string.h>
19#include <linux/init.h>
20#include <linux/bootmem.h>
21
22#include <asm/io.h>
23#include <asm/prom.h>
24#include <asm/pci-bridge.h>
25#include <asm/machdep.h>
26
27#include "mpc86xx.h"
28
29#define PCI_CFG_OUT out_be32
30
31/* ERRATA PCI-Ex 14 PCIE Controller timeout */
32#define PCIE_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
33
34
35static int
36indirect_read_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
37 int len, u32 *val)
38{
39 struct pci_controller *hose = bus->sysdata;
40 volatile void __iomem *cfg_data;
41 u32 temp;
42
43 if (ppc_md.pci_exclude_device)
44 if (ppc_md.pci_exclude_device(bus->number, devfn))
45 return PCIBIOS_DEVICE_NOT_FOUND;
46
47 /* Possible artifact of CDCpp50937 needs further investigation */
48 if (devfn != 0x0 && bus->number == 0xff)
49 return PCIBIOS_DEVICE_NOT_FOUND;
50
51 PCIE_FIX;
52 if (bus->number == 0xff) {
53 PCI_CFG_OUT(hose->cfg_addr,
54 (0x80000000 | ((offset & 0xf00) << 16) |
55 ((bus->number - hose->bus_offset) << 16)
56 | (devfn << 8) | ((offset & 0xfc) )));
57 } else {
58 PCI_CFG_OUT(hose->cfg_addr,
59 (0x80000001 | ((offset & 0xf00) << 16) |
60 ((bus->number - hose->bus_offset) << 16)
61 | (devfn << 8) | ((offset & 0xfc) )));
62 }
63
64 /*
65 * Note: the caller has already checked that offset is
66 * suitably aligned and that len is 1, 2 or 4.
67 */
68 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
69 cfg_data = hose->cfg_data;
70 PCIE_FIX;
71 temp = in_le32(cfg_data);
72 switch (len) {
73 case 1:
74 *val = (temp >> (((offset & 3))*8)) & 0xff;
75 break;
76 case 2:
77 *val = (temp >> (((offset & 3))*8)) & 0xffff;
78 break;
79 default:
80 *val = temp;
81 break;
82 }
83 return PCIBIOS_SUCCESSFUL;
84}
85
86static int
87indirect_write_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
88 int len, u32 val)
89{
90 struct pci_controller *hose = bus->sysdata;
91 volatile void __iomem *cfg_data;
92 u32 temp;
93
94 if (ppc_md.pci_exclude_device)
95 if (ppc_md.pci_exclude_device(bus->number, devfn))
96 return PCIBIOS_DEVICE_NOT_FOUND;
97
98 /* Possible artifact of CDCpp50937 needs further investigation */
99 if (devfn != 0x0 && bus->number == 0xff)
100 return PCIBIOS_DEVICE_NOT_FOUND;
101
102 PCIE_FIX;
103 if (bus->number == 0xff) {
104 PCI_CFG_OUT(hose->cfg_addr,
105 (0x80000000 | ((offset & 0xf00) << 16) |
106 ((bus->number - hose->bus_offset) << 16)
107 | (devfn << 8) | ((offset & 0xfc) )));
108 } else {
109 PCI_CFG_OUT(hose->cfg_addr,
110 (0x80000001 | ((offset & 0xf00) << 16) |
111 ((bus->number - hose->bus_offset) << 16)
112 | (devfn << 8) | ((offset & 0xfc) )));
113 }
114
115 /*
116 * Note: the caller has already checked that offset is
117 * suitably aligned and that len is 1, 2 or 4.
118 */
119 /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
120 cfg_data = hose->cfg_data;
121 switch (len) {
122 case 1:
123 PCIE_FIX;
124 temp = in_le32(cfg_data);
125 temp = (temp & ~(0xff << ((offset & 3) * 8))) |
126 (val << ((offset & 3) * 8));
127 PCIE_FIX;
128 out_le32(cfg_data, temp);
129 break;
130 case 2:
131 PCIE_FIX;
132 temp = in_le32(cfg_data);
133 temp = (temp & ~(0xffff << ((offset & 3) * 8)));
134 temp |= (val << ((offset & 3) * 8)) ;
135 PCIE_FIX;
136 out_le32(cfg_data, temp);
137 break;
138 default:
139 PCIE_FIX;
140 out_le32(cfg_data, val);
141 break;
142 }
143 PCIE_FIX;
144 return PCIBIOS_SUCCESSFUL;
145}
146
147static struct pci_ops indirect_pcie_ops = {
148 indirect_read_config_pcie,
149 indirect_write_config_pcie
150};
151
152void __init
153setup_indirect_pcie_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
154 void __iomem * cfg_data)
155{
156 hose->cfg_addr = cfg_addr;
157 hose->cfg_data = cfg_data;
158 hose->ops = &indirect_pcie_ops;
159}
160
161void __init
162setup_indirect_pcie(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
163{
164 unsigned long base = cfg_addr & PAGE_MASK;
165 void __iomem *mbase, *addr, *data;
166
167 mbase = ioremap(base, PAGE_SIZE);
168 addr = mbase + (cfg_addr & ~PAGE_MASK);
169 if ((cfg_data & PAGE_MASK) != base)
170 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
171 data = mbase + (cfg_data & ~PAGE_MASK);
172 setup_indirect_pcie_nomap(hose, addr, data);
173}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 20:36:17 -0500