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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-07-12 23:38:26 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-07-12 23:38:26 -0400
commitaf3bf7fbe0148aadc8fedd6f5e5279cabef9ced5 (patch)
tree25e3b1099ecf851bb7b5f6e6d3ffcdeb33de32f0 /arch/powerpc/platforms/85xx
parent10db8d212864cb6741df7d7fafda5ab6661f6f88 (diff)
parentb915341b4be29b3b2c02da932b69871e9b55ca4b (diff)
Merge remote-tracking branch 'kumar/next' into next
Freescale updates for 3.6
Diffstat (limited to 'arch/powerpc/platforms/85xx')
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig43
-rw-r--r--arch/powerpc/platforms/85xx/Makefile4
-rw-r--r--arch/powerpc/platforms/85xx/bsc913x_rdb.c67
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ds.c97
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_rdb.c22
-rw-r--r--arch/powerpc/platforms/85xx/p1022_ds.c106
-rw-r--r--arch/powerpc/platforms/85xx/p3060_qds.c77
-rw-r--r--arch/powerpc/platforms/85xx/qemu_e500.c72
-rw-r--r--arch/powerpc/platforms/85xx/sbc8560.c254
9 files changed, 310 insertions, 432 deletions
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index f000d81c4e31..159c01e91463 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -23,6 +23,15 @@ config FSL_85XX_CACHE_SRAM
23 cache-sram-size and cache-sram-offset kernel boot 23 cache-sram-size and cache-sram-offset kernel boot
24 parameters should be passed when this option is enabled. 24 parameters should be passed when this option is enabled.
25 25
26config BSC9131_RDB
27 bool "Freescale BSC9131RDB"
28 select DEFAULT_UIMAGE
29 help
30 This option enables support for the Freescale BSC9131RDB board.
31 The BSC9131 is a heterogeneous SoC containing an e500v2 powerpc and a
32 StarCore SC3850 DSP
33 Manufacturer : Freescale Semiconductor, Inc
34
26config MPC8540_ADS 35config MPC8540_ADS
27 bool "Freescale MPC8540 ADS" 36 bool "Freescale MPC8540 ADS"
28 select DEFAULT_UIMAGE 37 select DEFAULT_UIMAGE
@@ -175,12 +184,6 @@ config SBC8548
175 help 184 help
176 This option enables support for the Wind River SBC8548 board 185 This option enables support for the Wind River SBC8548 board
177 186
178config SBC8560
179 bool "Wind River SBC8560"
180 select DEFAULT_UIMAGE
181 help
182 This option enables support for the Wind River SBC8560 board
183
184config GE_IMP3A 187config GE_IMP3A
185 bool "GE Intelligent Platforms IMP3A" 188 bool "GE Intelligent Platforms IMP3A"
186 select DEFAULT_UIMAGE 189 select DEFAULT_UIMAGE
@@ -222,18 +225,6 @@ config P3041_DS
222 help 225 help
223 This option enables support for the P3041 DS board 226 This option enables support for the P3041 DS board
224 227
225config P3060_QDS
226 bool "Freescale P3060 QDS"
227 select DEFAULT_UIMAGE
228 select PPC_E500MC
229 select PHYS_64BIT
230 select SWIOTLB
231 select GPIO_MPC8XXX
232 select HAS_RAPIDIO
233 select PPC_EPAPR_HV_PIC
234 help
235 This option enables support for the P3060 QDS board
236
237config P4080_DS 228config P4080_DS
238 bool "Freescale P4080 DS" 229 bool "Freescale P4080 DS"
239 select DEFAULT_UIMAGE 230 select DEFAULT_UIMAGE
@@ -263,6 +254,22 @@ config P5020_DS
263 help 254 help
264 This option enables support for the P5020 DS board 255 This option enables support for the P5020 DS board
265 256
257config PPC_QEMU_E500
258 bool "QEMU generic e500 platform"
259 depends on EXPERIMENTAL
260 select DEFAULT_UIMAGE
261 help
262 This option enables support for running as a QEMU guest using
263 QEMU's generic e500 machine. This is not required if you're
264 using a QEMU machine that targets a specific board, such as
265 mpc8544ds.
266
267 Unlike most e500 boards that target a specific CPU, this
268 platform works with any e500-family CPU that QEMU supports.
269 Thus, you'll need to make sure CONFIG_PPC_E500MC is set or
270 unset based on the emulated CPU (or actual host CPU in the case
271 of KVM).
272
266endif # FSL_SOC_BOOKE 273endif # FSL_SOC_BOOKE
267 274
268config TQM85xx 275config TQM85xx
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 2125d4ca068a..3dfe81175036 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_SMP) += smp.o
5 5
6obj-y += common.o 6obj-y += common.o
7 7
8obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
8obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o 9obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
9obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o 10obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
10obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o 11obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
@@ -17,14 +18,13 @@ obj-$(CONFIG_P1022_DS) += p1022_ds.o
17obj-$(CONFIG_P1023_RDS) += p1023_rds.o 18obj-$(CONFIG_P1023_RDS) += p1023_rds.o
18obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o 19obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
19obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o 20obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
20obj-$(CONFIG_P3060_QDS) += p3060_qds.o corenet_ds.o
21obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o 21obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
22obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o 22obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
23obj-$(CONFIG_STX_GP3) += stx_gp3.o 23obj-$(CONFIG_STX_GP3) += stx_gp3.o
24obj-$(CONFIG_TQM85xx) += tqm85xx.o 24obj-$(CONFIG_TQM85xx) += tqm85xx.o
25obj-$(CONFIG_SBC8560) += sbc8560.o
26obj-$(CONFIG_SBC8548) += sbc8548.o 25obj-$(CONFIG_SBC8548) += sbc8548.o
27obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o 26obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
28obj-$(CONFIG_KSI8560) += ksi8560.o 27obj-$(CONFIG_KSI8560) += ksi8560.o
29obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o 28obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
30obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o 29obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
30obj-$(CONFIG_PPC_QEMU_E500) += qemu_e500.o
diff --git a/arch/powerpc/platforms/85xx/bsc913x_rdb.c b/arch/powerpc/platforms/85xx/bsc913x_rdb.c
new file mode 100644
index 000000000000..9d57bedb940c
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/bsc913x_rdb.c
@@ -0,0 +1,67 @@
1/*
2 * BSC913xRDB Board Setup
3 *
4 * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
5 *
6 * Copyright 2011-2012 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/of_platform.h>
15#include <linux/pci.h>
16#include <asm/mpic.h>
17#include <sysdev/fsl_soc.h>
18#include <asm/udbg.h>
19
20#include "mpc85xx.h"
21
22void __init bsc913x_rdb_pic_init(void)
23{
24 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
25 MPIC_SINGLE_DEST_CPU,
26 0, 256, " OpenPIC ");
27
28 if (!mpic)
29 pr_err("bsc913x: Failed to allocate MPIC structure\n");
30 else
31 mpic_init(mpic);
32}
33
34/*
35 * Setup the architecture
36 */
37static void __init bsc913x_rdb_setup_arch(void)
38{
39 if (ppc_md.progress)
40 ppc_md.progress("bsc913x_rdb_setup_arch()", 0);
41
42 pr_info("bsc913x board from Freescale Semiconductor\n");
43}
44
45machine_device_initcall(bsc9131_rdb, mpc85xx_common_publish_devices);
46
47/*
48 * Called very early, device-tree isn't unflattened
49 */
50
51static int __init bsc9131_rdb_probe(void)
52{
53 unsigned long root = of_get_flat_dt_root();
54
55 return of_flat_dt_is_compatible(root, "fsl,bsc9131rdb");
56}
57
58define_machine(bsc9131_rdb) {
59 .name = "BSC9131 RDB",
60 .probe = bsc9131_rdb_probe,
61 .setup_arch = bsc913x_rdb_setup_arch,
62 .init_IRQ = bsc913x_rdb_pic_init,
63 .get_irq = mpic_get_irq,
64 .restart = fsl_rstcr_restart,
65 .calibrate_decr = generic_calibrate_decr,
66 .progress = udbg_progress,
67};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index d30f6c47917d..6d3265fe7718 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -114,71 +114,53 @@ void __init mpc85xx_ds_pic_init(void)
114} 114}
115 115
116#ifdef CONFIG_PCI 116#ifdef CONFIG_PCI
117static int primary_phb_addr;
118extern int uli_exclude_device(struct pci_controller *hose, 117extern int uli_exclude_device(struct pci_controller *hose,
119 u_char bus, u_char devfn); 118 u_char bus, u_char devfn);
120 119
120static struct device_node *pci_with_uli;
121
121static int mpc85xx_exclude_device(struct pci_controller *hose, 122static int mpc85xx_exclude_device(struct pci_controller *hose,
122 u_char bus, u_char devfn) 123 u_char bus, u_char devfn)
123{ 124{
124 struct device_node* node; 125 if (hose->dn == pci_with_uli)
125 struct resource rsrc;
126
127 node = hose->dn;
128 of_address_to_resource(node, 0, &rsrc);
129
130 if ((rsrc.start & 0xfffff) == primary_phb_addr) {
131 return uli_exclude_device(hose, bus, devfn); 126 return uli_exclude_device(hose, bus, devfn);
132 }
133 127
134 return PCIBIOS_SUCCESSFUL; 128 return PCIBIOS_SUCCESSFUL;
135} 129}
136#endif /* CONFIG_PCI */ 130#endif /* CONFIG_PCI */
137 131
138/* 132static void __init mpc85xx_ds_pci_init(void)
139 * Setup the architecture
140 */
141static void __init mpc85xx_ds_setup_arch(void)
142{ 133{
143#ifdef CONFIG_PCI 134#ifdef CONFIG_PCI
144 struct device_node *np; 135 struct device_node *node;
145 struct pci_controller *hose;
146#endif
147 dma_addr_t max = 0xffffffff;
148 136
149 if (ppc_md.progress) 137 fsl_pci_init();
150 ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
151 138
152#ifdef CONFIG_PCI 139 /* See if we have a ULI under the primary */
153 for_each_node_by_type(np, "pci") { 140
154 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || 141 node = of_find_node_by_name(NULL, "uli1575");
155 of_device_is_compatible(np, "fsl,mpc8548-pcie") || 142 while ((pci_with_uli = of_get_parent(node))) {
156 of_device_is_compatible(np, "fsl,p2020-pcie")) { 143 of_node_put(node);
157 struct resource rsrc; 144 node = pci_with_uli;
158 of_address_to_resource(np, 0, &rsrc); 145
159 if ((rsrc.start & 0xfffff) == primary_phb_addr) 146 if (pci_with_uli == fsl_pci_primary) {
160 fsl_add_bridge(np, 1); 147 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
161 else 148 break;
162 fsl_add_bridge(np, 0);
163
164 hose = pci_find_hose_for_OF_device(np);
165 max = min(max, hose->dma_window_base_cur +
166 hose->dma_window_size);
167 } 149 }
168 } 150 }
169
170 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
171#endif 151#endif
152}
172 153
173 mpc85xx_smp_init(); 154/*
155 * Setup the architecture
156 */
157static void __init mpc85xx_ds_setup_arch(void)
158{
159 if (ppc_md.progress)
160 ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
174 161
175#ifdef CONFIG_SWIOTLB 162 mpc85xx_ds_pci_init();
176 if ((memblock_end_of_DRAM() - 1) > max) { 163 mpc85xx_smp_init();
177 ppc_swiotlb_enable = 1;
178 set_pci_dma_ops(&swiotlb_dma_ops);
179 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
180 }
181#endif
182 164
183 printk("MPC85xx DS board from Freescale Semiconductor\n"); 165 printk("MPC85xx DS board from Freescale Semiconductor\n");
184} 166}
@@ -190,14 +172,7 @@ static int __init mpc8544_ds_probe(void)
190{ 172{
191 unsigned long root = of_get_flat_dt_root(); 173 unsigned long root = of_get_flat_dt_root();
192 174
193 if (of_flat_dt_is_compatible(root, "MPC8544DS")) { 175 return !!of_flat_dt_is_compatible(root, "MPC8544DS");
194#ifdef CONFIG_PCI
195 primary_phb_addr = 0xb000;
196#endif
197 return 1;
198 }
199
200 return 0;
201} 176}
202 177
203machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices); 178machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
@@ -215,14 +190,7 @@ static int __init mpc8572_ds_probe(void)
215{ 190{
216 unsigned long root = of_get_flat_dt_root(); 191 unsigned long root = of_get_flat_dt_root();
217 192
218 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) { 193 return !!of_flat_dt_is_compatible(root, "fsl,MPC8572DS");
219#ifdef CONFIG_PCI
220 primary_phb_addr = 0x8000;
221#endif
222 return 1;
223 }
224
225 return 0;
226} 194}
227 195
228/* 196/*
@@ -232,14 +200,7 @@ static int __init p2020_ds_probe(void)
232{ 200{
233 unsigned long root = of_get_flat_dt_root(); 201 unsigned long root = of_get_flat_dt_root();
234 202
235 if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) { 203 return !!of_flat_dt_is_compatible(root, "fsl,P2020DS");
236#ifdef CONFIG_PCI
237 primary_phb_addr = 0x9000;
238#endif
239 return 1;
240 }
241
242 return 0;
243} 204}
244 205
245define_machine(mpc8544_ds) { 206define_machine(mpc8544_ds) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 313fce4f5574..1910fdcb75b2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -169,6 +169,7 @@ machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
169machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 169machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
170machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 170machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
171machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices); 171machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
172machine_device_initcall(p1024_rdb, mpc85xx_common_publish_devices);
172 173
173/* 174/*
174 * Called very early, device-tree isn't unflattened 175 * Called very early, device-tree isn't unflattened
@@ -237,6 +238,13 @@ static int __init p1020_utm_pc_probe(void)
237 return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC"); 238 return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC");
238} 239}
239 240
241static int __init p1024_rdb_probe(void)
242{
243 unsigned long root = of_get_flat_dt_root();
244
245 return of_flat_dt_is_compatible(root, "fsl,P1024RDB");
246}
247
240define_machine(p2020_rdb) { 248define_machine(p2020_rdb) {
241 .name = "P2020 RDB", 249 .name = "P2020 RDB",
242 .probe = p2020_rdb_probe, 250 .probe = p2020_rdb_probe,
@@ -348,3 +356,17 @@ define_machine(p1020_rdb_pc) {
348 .calibrate_decr = generic_calibrate_decr, 356 .calibrate_decr = generic_calibrate_decr,
349 .progress = udbg_progress, 357 .progress = udbg_progress,
350}; 358};
359
360define_machine(p1024_rdb) {
361 .name = "P1024 RDB",
362 .probe = p1024_rdb_probe,
363 .setup_arch = mpc85xx_rdb_setup_arch,
364 .init_IRQ = mpc85xx_rdb_pic_init,
365#ifdef CONFIG_PCI
366 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
367#endif
368 .get_irq = mpic_get_irq,
369 .restart = fsl_rstcr_restart,
370 .calibrate_decr = generic_calibrate_decr,
371 .progress = udbg_progress,
372};
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 31d18b964f94..89ee02c54561 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -27,6 +27,7 @@
27#include <sysdev/fsl_pci.h> 27#include <sysdev/fsl_pci.h>
28#include <asm/udbg.h> 28#include <asm/udbg.h>
29#include <asm/fsl_guts.h> 29#include <asm/fsl_guts.h>
30#include <asm/fsl_lbc.h>
30#include "smp.h" 31#include "smp.h"
31 32
32#include "mpc85xx.h" 33#include "mpc85xx.h"
@@ -142,17 +143,73 @@ static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
142{ 143{
143} 144}
144 145
146struct fsl_law {
147 u32 lawbar;
148 u32 reserved1;
149 u32 lawar;
150 u32 reserved[5];
151};
152
153#define LAWBAR_MASK 0x00F00000
154#define LAWBAR_SHIFT 12
155
156#define LAWAR_EN 0x80000000
157#define LAWAR_TGT_MASK 0x01F00000
158#define LAW_TRGT_IF_LBC (0x04 << 20)
159
160#define LAWAR_MASK (LAWAR_EN | LAWAR_TGT_MASK)
161#define LAWAR_MATCH (LAWAR_EN | LAW_TRGT_IF_LBC)
162
163#define BR_BA 0xFFFF8000
164
165/*
166 * Map a BRx value to a physical address
167 *
168 * The localbus BRx registers only store the lower 32 bits of the address. To
169 * obtain the upper four bits, we need to scan the LAW table. The entry which
170 * maps to the localbus will contain the upper four bits.
171 */
172static phys_addr_t lbc_br_to_phys(const void *ecm, unsigned int count, u32 br)
173{
174#ifndef CONFIG_PHYS_64BIT
175 /*
176 * If we only have 32-bit addressing, then the BRx address *is* the
177 * physical address.
178 */
179 return br & BR_BA;
180#else
181 const struct fsl_law *law = ecm + 0xc08;
182 unsigned int i;
183
184 for (i = 0; i < count; i++) {
185 u64 lawbar = in_be32(&law[i].lawbar);
186 u32 lawar = in_be32(&law[i].lawar);
187
188 if ((lawar & LAWAR_MASK) == LAWAR_MATCH)
189 /* Extract the upper four bits */
190 return (br & BR_BA) | ((lawbar & LAWBAR_MASK) << 12);
191 }
192
193 return 0;
194#endif
195}
196
145/** 197/**
146 * p1022ds_set_monitor_port: switch the output to a different monitor port 198 * p1022ds_set_monitor_port: switch the output to a different monitor port
147 *
148 */ 199 */
149static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port) 200static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
150{ 201{
151 struct device_node *guts_node; 202 struct device_node *guts_node;
152 struct device_node *indirect_node = NULL; 203 struct device_node *lbc_node = NULL;
204 struct device_node *law_node = NULL;
153 struct ccsr_guts __iomem *guts; 205 struct ccsr_guts __iomem *guts;
206 struct fsl_lbc_regs *lbc = NULL;
207 void *ecm = NULL;
154 u8 __iomem *lbc_lcs0_ba = NULL; 208 u8 __iomem *lbc_lcs0_ba = NULL;
155 u8 __iomem *lbc_lcs1_ba = NULL; 209 u8 __iomem *lbc_lcs1_ba = NULL;
210 phys_addr_t cs0_addr, cs1_addr;
211 const __be32 *iprop;
212 unsigned int num_laws;
156 u8 b; 213 u8 b;
157 214
158 /* Map the global utilities registers. */ 215 /* Map the global utilities registers. */
@@ -168,25 +225,43 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
168 goto exit; 225 goto exit;
169 } 226 }
170 227
171 indirect_node = of_find_compatible_node(NULL, NULL, 228 lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
172 "fsl,p1022ds-indirect-pixis"); 229 if (!lbc_node) {
173 if (!indirect_node) { 230 pr_err("p1022ds: missing localbus node\n");
174 pr_err("p1022ds: missing pixis indirect mode node\n");
175 goto exit; 231 goto exit;
176 } 232 }
177 233
178 lbc_lcs0_ba = of_iomap(indirect_node, 0); 234 lbc = of_iomap(lbc_node, 0);
179 if (!lbc_lcs0_ba) { 235 if (!lbc) {
180 pr_err("p1022ds: could not map localbus chip select 0\n"); 236 pr_err("p1022ds: could not map localbus node\n");
181 goto exit; 237 goto exit;
182 } 238 }
183 239
184 lbc_lcs1_ba = of_iomap(indirect_node, 1); 240 law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
185 if (!lbc_lcs1_ba) { 241 if (!law_node) {
186 pr_err("p1022ds: could not map localbus chip select 1\n"); 242 pr_err("p1022ds: missing local access window node\n");
187 goto exit; 243 goto exit;
188 } 244 }
189 245
246 ecm = of_iomap(law_node, 0);
247 if (!ecm) {
248 pr_err("p1022ds: could not map local access window node\n");
249 goto exit;
250 }
251
252 iprop = of_get_property(law_node, "fsl,num-laws", 0);
253 if (!iprop) {
254 pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
255 goto exit;
256 }
257 num_laws = be32_to_cpup(iprop);
258
259 cs0_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[0].br));
260 cs1_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[1].br));
261
262 lbc_lcs0_ba = ioremap(cs0_addr, 1);
263 lbc_lcs1_ba = ioremap(cs1_addr, 1);
264
190 /* Make sure we're in indirect mode first. */ 265 /* Make sure we're in indirect mode first. */
191 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) != 266 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
192 PMUXCR_ELBCDIU_DIU) { 267 PMUXCR_ELBCDIU_DIU) {
@@ -254,10 +329,15 @@ exit:
254 iounmap(lbc_lcs1_ba); 329 iounmap(lbc_lcs1_ba);
255 if (lbc_lcs0_ba) 330 if (lbc_lcs0_ba)
256 iounmap(lbc_lcs0_ba); 331 iounmap(lbc_lcs0_ba);
332 if (lbc)
333 iounmap(lbc);
334 if (ecm)
335 iounmap(ecm);
257 if (guts) 336 if (guts)
258 iounmap(guts); 337 iounmap(guts);
259 338
260 of_node_put(indirect_node); 339 of_node_put(law_node);
340 of_node_put(lbc_node);
261 of_node_put(guts_node); 341 of_node_put(guts_node);
262} 342}
263 343
diff --git a/arch/powerpc/platforms/85xx/p3060_qds.c b/arch/powerpc/platforms/85xx/p3060_qds.c
deleted file mode 100644
index 081cf4ac1881..000000000000
--- a/arch/powerpc/platforms/85xx/p3060_qds.c
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * P3060 QDS Setup
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/phy.h>
15#include <asm/machdep.h>
16#include <asm/udbg.h>
17#include <asm/mpic.h>
18#include <linux/of_platform.h>
19#include <sysdev/fsl_soc.h>
20#include <sysdev/fsl_pci.h>
21#include <asm/ehv_pic.h>
22#include "corenet_ds.h"
23
24/*
25 * Called very early, device-tree isn't unflattened
26 */
27static int __init p3060_qds_probe(void)
28{
29 unsigned long root = of_get_flat_dt_root();
30#ifdef CONFIG_SMP
31 extern struct smp_ops_t smp_85xx_ops;
32#endif
33
34 if (of_flat_dt_is_compatible(root, "fsl,P3060QDS"))
35 return 1;
36
37 /* Check if we're running under the Freescale hypervisor */
38 if (of_flat_dt_is_compatible(root, "fsl,P3060QDS-hv")) {
39 ppc_md.init_IRQ = ehv_pic_init;
40 ppc_md.get_irq = ehv_pic_get_irq;
41 ppc_md.restart = fsl_hv_restart;
42 ppc_md.power_off = fsl_hv_halt;
43 ppc_md.halt = fsl_hv_halt;
44#ifdef CONFIG_SMP
45 /*
46 * Disable the timebase sync operations because we can't write
47 * to the timebase registers under the hypervisor.
48 */
49 smp_85xx_ops.give_timebase = NULL;
50 smp_85xx_ops.take_timebase = NULL;
51#endif
52 return 1;
53 }
54
55 return 0;
56}
57
58define_machine(p3060_qds) {
59 .name = "P3060 QDS",
60 .probe = p3060_qds_probe,
61 .setup_arch = corenet_ds_setup_arch,
62 .init_IRQ = corenet_ds_pic_init,
63#ifdef CONFIG_PCI
64 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
65#endif
66 .get_irq = mpic_get_coreint_irq,
67 .restart = fsl_rstcr_restart,
68 .calibrate_decr = generic_calibrate_decr,
69 .progress = udbg_progress,
70 .power_save = e500_idle,
71};
72
73machine_device_initcall(p3060_qds, corenet_ds_publish_devices);
74
75#ifdef CONFIG_SWIOTLB
76machine_arch_initcall(p3060_qds, swiotlb_setup_bus_notifier);
77#endif
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
new file mode 100644
index 000000000000..95a2e53af71b
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -0,0 +1,72 @@
1/*
2 * Paravirt target for a generic QEMU e500 machine
3 *
4 * This is intended to be a flexible device-tree-driven platform, not fixed
5 * to a particular piece of hardware or a particular spec of virtual hardware,
6 * beyond the assumption of an e500-family CPU. Some things are still hardcoded
7 * here, such as MPIC, but this is a limitation of the current code rather than
8 * an interface contract with QEMU.
9 *
10 * Copyright 2012 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/kernel.h>
19#include <linux/of_fdt.h>
20#include <asm/machdep.h>
21#include <asm/time.h>
22#include <asm/udbg.h>
23#include <asm/mpic.h>
24#include <sysdev/fsl_soc.h>
25#include <sysdev/fsl_pci.h>
26#include "smp.h"
27#include "mpc85xx.h"
28
29void __init qemu_e500_pic_init(void)
30{
31 struct mpic *mpic;
32
33 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,
34 0, 256, " OpenPIC ");
35
36 BUG_ON(mpic == NULL);
37 mpic_init(mpic);
38}
39
40static void __init qemu_e500_setup_arch(void)
41{
42 ppc_md.progress("qemu_e500_setup_arch()", 0);
43
44 fsl_pci_init();
45 mpc85xx_smp_init();
46}
47
48/*
49 * Called very early, device-tree isn't unflattened
50 */
51static int __init qemu_e500_probe(void)
52{
53 unsigned long root = of_get_flat_dt_root();
54
55 return !!of_flat_dt_is_compatible(root, "fsl,qemu-e500");
56}
57
58machine_device_initcall(qemu_e500, mpc85xx_common_publish_devices);
59
60define_machine(qemu_e500) {
61 .name = "QEMU e500",
62 .probe = qemu_e500_probe,
63 .setup_arch = qemu_e500_setup_arch,
64 .init_IRQ = qemu_e500_pic_init,
65#ifdef CONFIG_PCI
66 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
67#endif
68 .get_irq = mpic_get_irq,
69 .restart = fsl_rstcr_restart,
70 .calibrate_decr = generic_calibrate_decr,
71 .progress = udbg_progress,
72};
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
deleted file mode 100644
index b1be632ede43..000000000000
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ /dev/null
@@ -1,254 +0,0 @@
1/*
2 * Wind River SBC8560 setup and early boot code.
3 *
4 * Copyright 2007 Wind River Systems Inc.
5 *
6 * By Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * Based largely on the MPC8560ADS support - Copyright 2005 Freescale Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/kdev_t.h>
20#include <linux/delay.h>
21#include <linux/seq_file.h>
22#include <linux/of_platform.h>
23
24#include <asm/time.h>
25#include <asm/machdep.h>
26#include <asm/pci-bridge.h>
27#include <asm/mpic.h>
28#include <mm/mmu_decl.h>
29#include <asm/udbg.h>
30
31#include <sysdev/fsl_soc.h>
32#include <sysdev/fsl_pci.h>
33
34#include "mpc85xx.h"
35
36#ifdef CONFIG_CPM2
37#include <asm/cpm2.h>
38#include <sysdev/cpm2_pic.h>
39#endif
40
41static void __init sbc8560_pic_init(void)
42{
43 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
44 0, 256, " OpenPIC ");
45 BUG_ON(mpic == NULL);
46 mpic_init(mpic);
47
48 mpc85xx_cpm2_pic_init();
49}
50
51/*
52 * Setup the architecture
53 */
54#ifdef CONFIG_CPM2
55struct cpm_pin {
56 int port, pin, flags;
57};
58
59static const struct cpm_pin sbc8560_pins[] = {
60 /* SCC1 */
61 {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
62 {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
63 {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
64
65 /* SCC2 */
66 {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
67 {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
68 {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
69
70 /* FCC2 */
71 {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
72 {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
73 {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
74 {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
75 {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
76 {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
77 {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
78 {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
79 {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
80 {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
81 {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
82 {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
83 {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
84 {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
85 {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
86 {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
87
88 /* FCC3 */
89 {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
90 {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
91 {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
92 {1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
93 {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
94 {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
95 {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
96 {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
97 {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
98 {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
99 {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
100 {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
101 {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
102 {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
103 {2, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK16 */
104 {2, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK15 */
105};
106
107static void __init init_ioports(void)
108{
109 int i;
110
111 for (i = 0; i < ARRAY_SIZE(sbc8560_pins); i++) {
112 const struct cpm_pin *pin = &sbc8560_pins[i];
113 cpm2_set_pin(pin->port, pin->pin, pin->flags);
114 }
115
116 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
117 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
118 cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
119 cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
120 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
121 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
122 cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
123 cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
124}
125#endif
126
127static void __init sbc8560_setup_arch(void)
128{
129#ifdef CONFIG_PCI
130 struct device_node *np;
131#endif
132
133 if (ppc_md.progress)
134 ppc_md.progress("sbc8560_setup_arch()", 0);
135
136#ifdef CONFIG_CPM2
137 cpm2_reset();
138 init_ioports();
139#endif
140
141#ifdef CONFIG_PCI
142 for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
143 fsl_add_bridge(np, 1);
144#endif
145}
146
147static void sbc8560_show_cpuinfo(struct seq_file *m)
148{
149 uint pvid, svid, phid1;
150
151 pvid = mfspr(SPRN_PVR);
152 svid = mfspr(SPRN_SVR);
153
154 seq_printf(m, "Vendor\t\t: Wind River\n");
155 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
156 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
157
158 /* Display cpu Pll setting */
159 phid1 = mfspr(SPRN_HID1);
160 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
161}
162
163machine_device_initcall(sbc8560, mpc85xx_common_publish_devices);
164
165/*
166 * Called very early, device-tree isn't unflattened
167 */
168static int __init sbc8560_probe(void)
169{
170 unsigned long root = of_get_flat_dt_root();
171
172 return of_flat_dt_is_compatible(root, "SBC8560");
173}
174
175#ifdef CONFIG_RTC_DRV_M48T59
176static int __init sbc8560_rtc_init(void)
177{
178 struct device_node *np;
179 struct resource res;
180 struct platform_device *rtc_dev;
181
182 np = of_find_compatible_node(NULL, NULL, "m48t59");
183 if (np == NULL) {
184 printk("No RTC in DTB. Has it been eaten by wild dogs?\n");
185 return -ENODEV;
186 }
187
188 of_address_to_resource(np, 0, &res);
189 of_node_put(np);
190
191 printk("Found RTC (m48t59) at i/o 0x%x\n", res.start);
192
193 rtc_dev = platform_device_register_simple("rtc-m48t59", 0, &res, 1);
194
195 if (IS_ERR(rtc_dev)) {
196 printk("Registering sbc8560 RTC device failed\n");
197 return PTR_ERR(rtc_dev);
198 }
199
200 return 0;
201}
202
203arch_initcall(sbc8560_rtc_init);
204
205#endif /* M48T59 */
206
207static __u8 __iomem *brstcr;
208
209static int __init sbc8560_bdrstcr_init(void)
210{
211 struct device_node *np;
212 struct resource res;
213
214 np = of_find_compatible_node(NULL, NULL, "wrs,sbc8560-brstcr");
215 if (np == NULL) {
216 printk(KERN_WARNING "sbc8560: No board specific RSTCR in DTB.\n");
217 return -ENODEV;
218 }
219
220 of_address_to_resource(np, 0, &res);
221
222 printk(KERN_INFO "sbc8560: Found BRSTCR at %pR\n", &res);
223
224 brstcr = ioremap(res.start, resource_size(&res));
225 if(!brstcr)
226 printk(KERN_WARNING "sbc8560: ioremap of brstcr failed.\n");
227
228 of_node_put(np);
229
230 return 0;
231}
232
233arch_initcall(sbc8560_bdrstcr_init);
234
235void sbc8560_rstcr_restart(char * cmd)
236{
237 local_irq_disable();
238 if(brstcr)
239 clrbits8(brstcr, 0x80);
240
241 while(1);
242}
243
244define_machine(sbc8560) {
245 .name = "SBC8560",
246 .probe = sbc8560_probe,
247 .setup_arch = sbc8560_setup_arch,
248 .init_IRQ = sbc8560_pic_init,
249 .show_cpuinfo = sbc8560_show_cpuinfo,
250 .get_irq = mpic_get_irq,
251 .restart = sbc8560_rstcr_restart,
252 .calibrate_decr = generic_calibrate_decr,
253 .progress = udbg_progress,
254};