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authorPaul Mackerras <paulus@samba.org>2006-08-25 00:56:07 -0400
committerPaul Mackerras <paulus@samba.org>2006-08-25 00:56:07 -0400
commitea0763a7e62f60f3e166327268a80f16ad806718 (patch)
treede54ec5e5d5a49b3cba81b096b7572852aa6f5a9 /arch/powerpc/platforms/85xx
parent271c511db9d37d6797745adb1f151a8bd2838c6f (diff)
parentc85c41ad73c6db4cf4cc98c595cc5e2fdbdb53d5 (diff)
Merge branch 'merge'
Diffstat (limited to 'arch/powerpc/platforms/85xx')
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ads.c162
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_cds.c210
3 files changed, 143 insertions, 230 deletions
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 454fc53289ab..c3268d9877e4 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -14,7 +14,6 @@ config MPC8540_ADS
14config MPC85xx_CDS 14config MPC85xx_CDS
15 bool "Freescale MPC85xx CDS" 15 bool "Freescale MPC85xx CDS"
16 select DEFAULT_UIMAGE 16 select DEFAULT_UIMAGE
17 select PPC_I8259 if PCI
18 help 17 help
19 This option enables support for the MPC85xx CDS board 18 This option enables support for the MPC85xx CDS board
20 19
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index d0cfcdb1d1b5..cae6b73357d5 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -37,79 +37,7 @@ unsigned long isa_io_base = 0;
37unsigned long isa_mem_base = 0; 37unsigned long isa_mem_base = 0;
38#endif 38#endif
39 39
40/*
41 * Internal interrupts are all Level Sensitive, and Positive Polarity
42 *
43 * Note: Likely, this table and the following function should be
44 * obtained and derived from the OF Device Tree.
45 */
46static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
47 MPC85XX_INTERNAL_IRQ_SENSES,
48 0x0, /* External 0: */
49#if defined(CONFIG_PCI)
50 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 0 */
51 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 1 */
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 2 */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 4: PCI slot 3 */
54#else
55 0x0, /* External 1: */
56 0x0, /* External 2: */
57 0x0, /* External 3: */
58 0x0, /* External 4: */
59#endif
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
61 0x0, /* External 6: */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
63 0x0, /* External 8: */
64 0x0, /* External 9: */
65 0x0, /* External 10: */
66 0x0, /* External 11: */
67};
68
69#ifdef CONFIG_PCI 40#ifdef CONFIG_PCI
70/*
71 * interrupt routing
72 */
73
74int
75mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
76{
77 static char pci_irq_table[][4] =
78 /*
79 * This is little evil, but works around the fact
80 * that revA boards have IDSEL starting at 18
81 * and others boards (older) start at 12
82 *
83 * PCI IDSEL/INTPIN->INTLINE
84 * A B C D
85 */
86 {
87 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */
88 {PIRQD, PIRQA, PIRQB, PIRQC},
89 {PIRQC, PIRQD, PIRQA, PIRQB},
90 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */
91 {0, 0, 0, 0}, /* -- */
92 {0, 0, 0, 0}, /* -- */
93 {0, 0, 0, 0}, /* -- */
94 {0, 0, 0, 0}, /* -- */
95 {0, 0, 0, 0}, /* -- */
96 {0, 0, 0, 0}, /* -- */
97 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */
98 {PIRQD, PIRQA, PIRQB, PIRQC},
99 {PIRQC, PIRQD, PIRQA, PIRQB},
100 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */
101 {0, 0, 0, 0}, /* -- */
102 {0, 0, 0, 0}, /* -- */
103 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */
104 {PIRQD, PIRQA, PIRQB, PIRQC},
105 {PIRQC, PIRQD, PIRQA, PIRQB},
106 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */
107 };
108
109 const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
110 return PCI_IRQ_TABLE_LOOKUP;
111}
112
113int 41int
114mpc85xx_exclude_device(u_char bus, u_char devfn) 42mpc85xx_exclude_device(u_char bus, u_char devfn)
115{ 43{
@@ -119,44 +47,63 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
119 return PCIBIOS_SUCCESSFUL; 47 return PCIBIOS_SUCCESSFUL;
120} 48}
121 49
50void __init
51mpc85xx_pcibios_fixup(void)
52{
53 struct pci_dev *dev = NULL;
54
55 for_each_pci_dev(dev)
56 pci_read_irq_line(dev);
57}
122#endif /* CONFIG_PCI */ 58#endif /* CONFIG_PCI */
123 59
124 60
125void __init mpc85xx_ads_pic_init(void) 61void __init mpc85xx_ads_pic_init(void)
126{ 62{
127 struct mpic *mpic1; 63 struct mpic *mpic;
128 phys_addr_t OpenPIC_PAddr; 64 struct resource r;
129 65 struct device_node *np = NULL;
130 /* Determine the Physical Address of the OpenPIC regs */ 66
131 OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET; 67 np = of_find_node_by_type(np, "open-pic");
132 68
133 mpic1 = mpic_alloc(OpenPIC_PAddr, 69 if (np == NULL) {
134 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 70 printk(KERN_ERR "Could not find open-pic node\n");
135 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250, 71 return;
136 mpc85xx_ads_openpic_initsenses, 72 }
137 sizeof(mpc85xx_ads_openpic_initsenses), 73
138 " OpenPIC "); 74 if(of_address_to_resource(np, 0, &r)) {
139 BUG_ON(mpic1 == NULL); 75 printk(KERN_ERR "Could not map mpic register space\n");
140 mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200); 76 of_node_put(np);
141 mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280); 77 return;
142 mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300); 78 }
143 mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380); 79
144 mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400); 80 mpic = mpic_alloc(np, r.start,
145 mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480); 81 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
146 mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500); 82 4, 0, " OpenPIC ");
147 mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580); 83 BUG_ON(mpic == NULL);
148 84 of_node_put(np);
149 /* dummy mappings to get to 48 */ 85
150 mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600); 86 mpic_assign_isu(mpic, 0, r.start + 0x10200);
151 mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680); 87 mpic_assign_isu(mpic, 1, r.start + 0x10280);
152 mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700); 88 mpic_assign_isu(mpic, 2, r.start + 0x10300);
153 mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780); 89 mpic_assign_isu(mpic, 3, r.start + 0x10380);
154 90 mpic_assign_isu(mpic, 4, r.start + 0x10400);
155 /* External ints */ 91 mpic_assign_isu(mpic, 5, r.start + 0x10480);
156 mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000); 92 mpic_assign_isu(mpic, 6, r.start + 0x10500);
157 mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080); 93 mpic_assign_isu(mpic, 7, r.start + 0x10580);
158 mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100); 94
159 mpic_init(mpic1); 95 /* Unused on this platform (leave room for 8548) */
96 mpic_assign_isu(mpic, 8, r.start + 0x10600);
97 mpic_assign_isu(mpic, 9, r.start + 0x10680);
98 mpic_assign_isu(mpic, 10, r.start + 0x10700);
99 mpic_assign_isu(mpic, 11, r.start + 0x10780);
100
101 /* External Interrupts */
102 mpic_assign_isu(mpic, 12, r.start + 0x10000);
103 mpic_assign_isu(mpic, 13, r.start + 0x10080);
104 mpic_assign_isu(mpic, 14, r.start + 0x10100);
105
106 mpic_init(mpic);
160} 107}
161 108
162/* 109/*
@@ -165,7 +112,9 @@ void __init mpc85xx_ads_pic_init(void)
165static void __init mpc85xx_ads_setup_arch(void) 112static void __init mpc85xx_ads_setup_arch(void)
166{ 113{
167 struct device_node *cpu; 114 struct device_node *cpu;
115#ifdef CONFIG_PCI
168 struct device_node *np; 116 struct device_node *np;
117#endif
169 118
170 if (ppc_md.progress) 119 if (ppc_md.progress)
171 ppc_md.progress("mpc85xx_ads_setup_arch()", 0); 120 ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
@@ -186,8 +135,7 @@ static void __init mpc85xx_ads_setup_arch(void)
186 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 135 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
187 add_bridge(np); 136 add_bridge(np);
188 137
189 ppc_md.pci_swizzle = common_swizzle; 138 ppc_md.pcibios_fixup = mpc85xx_pcibios_fixup;
190 ppc_md.pci_map_irq = mpc85xx_map_irq;
191 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 139 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
192#endif 140#endif
193 141
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 5fd53eba6912..4c1fede6470e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -57,94 +57,8 @@ unsigned long isa_mem_base = 0;
57static int cds_pci_slot = 2; 57static int cds_pci_slot = 2;
58static volatile u8 *cadmus; 58static volatile u8 *cadmus;
59 59
60/*
61 * Internal interrupts are all Level Sensitive, and Positive Polarity
62 *
63 * Note: Likely, this table and the following function should be
64 * obtained and derived from the OF Device Tree.
65 */
66static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
67 MPC85XX_INTERNAL_IRQ_SENSES,
68#if defined(CONFIG_PCI)
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Ext 0: PCI slot 0 */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 1 */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 2 */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 3 */
73#else
74 0x0, /* External 0: */
75 0x0, /* External 1: */
76 0x0, /* External 2: */
77 0x0, /* External 3: */
78#endif
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
80 0x0, /* External 6: */
81 0x0, /* External 7: */
82 0x0, /* External 8: */
83 0x0, /* External 9: */
84 0x0, /* External 10: */
85#ifdef CONFIG_PCI
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 11: PCI2 slot 0 */
87#else
88 0x0, /* External 11: */
89#endif
90};
91
92 60
93#ifdef CONFIG_PCI 61#ifdef CONFIG_PCI
94/*
95 * interrupt routing
96 */
97int
98mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
99{
100 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
101
102 if (!hose->index)
103 {
104 /* Handle PCI1 interrupts */
105 char pci_irq_table[][4] =
106 /*
107 * PCI IDSEL/INTPIN->INTLINE
108 * A B C D
109 */
110
111 /* Note IRQ assignment for slots is based on which slot the elysium is
112 * in -- in this setup elysium is in slot #2 (this PIRQA as first
113 * interrupt on slot */
114 {
115 { 0, 1, 2, 3 }, /* 16 - PMC */
116 { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
117 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
118 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
119 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
120 { 3, 0, 1, 2 }, /* 21 - Slot 4 */
121 };
122
123 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
124 int i, j;
125
126 for (i = 0; i < 6; i++)
127 for (j = 0; j < 4; j++)
128 pci_irq_table[i][j] =
129 ((pci_irq_table[i][j] + 5 -
130 cds_pci_slot) & 0x3) + PIRQ0A;
131
132 return PCI_IRQ_TABLE_LOOKUP;
133 } else {
134 /* Handle PCI2 interrupts (if we have one) */
135 char pci_irq_table[][4] =
136 {
137 /*
138 * We only have one slot and one interrupt
139 * going to PIRQA - PIRQD */
140 { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
141 };
142
143 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
144
145 return PCI_IRQ_TABLE_LOOKUP;
146 }
147}
148 62
149#define ARCADIA_HOST_BRIDGE_IDSEL 17 63#define ARCADIA_HOST_BRIDGE_IDSEL 17
150#define ARCADIA_2ND_BRIDGE_IDSEL 3 64#define ARCADIA_2ND_BRIDGE_IDSEL 3
@@ -210,50 +124,104 @@ mpc85xx_cds_pcibios_fixup(void)
210 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 124 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
211 pci_dev_put(dev); 125 pci_dev_put(dev);
212 } 126 }
127
128 /* Now map all the PCI irqs */
129 dev = NULL;
130 for_each_pci_dev(dev)
131 pci_read_irq_line(dev);
132}
133
134#ifdef CONFIG_PPC_I8259
135#warning The i8259 PIC support is currently broken
136static void mpc85xx_8259_cascade(unsigned int irq, struct
137 irq_desc *desc, struct pt_regs *regs)
138{
139 unsigned int cascade_irq = i8259_irq(regs);
140
141 if (cascade_irq != NO_IRQ)
142 generic_handle_irq(cascade_irq, regs);
143
144 desc->chip->eoi(irq);
213} 145}
146#endif /* PPC_I8259 */
214#endif /* CONFIG_PCI */ 147#endif /* CONFIG_PCI */
215 148
216void __init mpc85xx_cds_pic_init(void) 149void __init mpc85xx_cds_pic_init(void)
217{ 150{
218 struct mpic *mpic1; 151 struct mpic *mpic;
219 phys_addr_t OpenPIC_PAddr; 152 struct resource r;
153 struct device_node *np = NULL;
154 struct device_node *cascade_node = NULL;
155 int cascade_irq;
220 156
221 /* Determine the Physical Address of the OpenPIC regs */ 157 np = of_find_node_by_type(np, "open-pic");
222 OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET; 158
159 if (np == NULL) {
160 printk(KERN_ERR "Could not find open-pic node\n");
161 return;
162 }
223 163
224 mpic1 = mpic_alloc(OpenPIC_PAddr, 164 if (of_address_to_resource(np, 0, &r)) {
165 printk(KERN_ERR "Failed to map mpic register space\n");
166 of_node_put(np);
167 return;
168 }
169
170 mpic = mpic_alloc(np, r.start,
225 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 171 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
226 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250, 172 4, 0, " OpenPIC ");
227 mpc85xx_cds_openpic_initsenses, 173 BUG_ON(mpic == NULL);
228 sizeof(mpc85xx_cds_openpic_initsenses), " OpenPIC "); 174
229 BUG_ON(mpic1 == NULL); 175 /* Return the mpic node */
230 mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200); 176 of_node_put(np);
231 mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280); 177
232 mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300); 178 mpic_assign_isu(mpic, 0, r.start + 0x10200);
233 mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380); 179 mpic_assign_isu(mpic, 1, r.start + 0x10280);
234 mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400); 180 mpic_assign_isu(mpic, 2, r.start + 0x10300);
235 mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480); 181 mpic_assign_isu(mpic, 3, r.start + 0x10380);
236 mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500); 182 mpic_assign_isu(mpic, 4, r.start + 0x10400);
237 mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580); 183 mpic_assign_isu(mpic, 5, r.start + 0x10480);
238 184 mpic_assign_isu(mpic, 6, r.start + 0x10500);
239 /* dummy mappings to get to 48 */ 185 mpic_assign_isu(mpic, 7, r.start + 0x10580);
240 mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600); 186
241 mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680); 187 /* Used only for 8548 so far, but no harm in
242 mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700); 188 * allocating them for everyone */
243 mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780); 189 mpic_assign_isu(mpic, 8, r.start + 0x10600);
244 190 mpic_assign_isu(mpic, 9, r.start + 0x10680);
245 /* External ints */ 191 mpic_assign_isu(mpic, 10, r.start + 0x10700);
246 mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000); 192 mpic_assign_isu(mpic, 11, r.start + 0x10780);
247 mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080); 193
248 mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100); 194 /* External Interrupts */
249 195 mpic_assign_isu(mpic, 12, r.start + 0x10000);
250 mpic_init(mpic1); 196 mpic_assign_isu(mpic, 13, r.start + 0x10080);
197 mpic_assign_isu(mpic, 14, r.start + 0x10100);
198
199 mpic_init(mpic);
200
201#ifdef CONFIG_PPC_I8259
202 /* Initialize the i8259 controller */
203 for_each_node_by_type(np, "interrupt-controller")
204 if (device_is_compatible(np, "chrp,iic")) {
205 cascade_node = np;
206 break;
207 }
208
209 if (cascade_node == NULL) {
210 printk(KERN_DEBUG "Could not find i8259 PIC\n");
211 return;
212 }
251 213
252#ifdef CONFIG_PCI 214 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
253 mpic_setup_cascade(PIRQ0A, i8259_irq_cascade, NULL); 215 if (cascade_irq == NO_IRQ) {
216 printk(KERN_ERR "Failed to map cascade interrupt\n");
217 return;
218 }
254 219
255 i8259_init(0,0); 220 i8259_init(cascade_node, 0);
256#endif 221 of_node_put(cascade_node);
222
223 set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
224#endif /* CONFIG_PPC_I8259 */
257} 225}
258 226
259 227
@@ -298,8 +266,6 @@ mpc85xx_cds_setup_arch(void)
298 add_bridge(np); 266 add_bridge(np);
299 267
300 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup; 268 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
301 ppc_md.pci_swizzle = common_swizzle;
302 ppc_md.pci_map_irq = mpc85xx_map_irq;
303 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 269 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
304#endif 270#endif
305 271
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 11:02:35 -0500