Merge commit 'origin/master' into next

Manual merge of:
	drivers/char/hvc_console.c
	drivers/char/hvc_console.h

2 files changed, 4 insertions, 3 deletions

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 04af81e39bec..04d105d689f1 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -341,7 +341,8 @@ static void __init mpc85xx_mds_pic_init(void)
         }
 
         mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
+                        MPIC_BROKEN_FRR_NIRQS,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         of_node_put(np);
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index 1b426050a2f9..0125604d096e 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -80,8 +80,8 @@ static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
         printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
 
         ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
-        if (machine_is_compatible("MPC8540") ||
-            machine_is_compatible("MPC8560"))
+        if (of_machine_is_compatible("MPC8540") ||
+            of_machine_is_compatible("MPC8560"))
                 /*
                  * Assume L2 SRAM is used fully for cache, so set
                  * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).