[PATCH] powerpc: Add MPC834x SYS board to arch/powerpc

Add the first MPC83xx board that uses a flat device tree to arch/powerpc.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

5 files changed, 380 insertions, 0 deletions

diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index b20812d460e6..7675e675dce1 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -7,6 +7,7 @@ choice
 
 config MPC834x_SYS
         bool "Freescale MPC834x SYS"
+        select DEFAULT_UIMAGE
         help
           This option enables support for the MPC 834x SYS evaluation board.
 
diff --git a/arch/powerpc/platforms/83xx/mpc834x_sys.c b/arch/powerpc/platforms/83xx/mpc834x_sys.c
new file mode 100644
index 000000000000..2098dd05a773
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc834x_sys.c
@@ -0,0 +1,243 @@
+/*
+ * arch/powerpc/platforms/83xx/mpc834x_sys.c
+ *
+ * MPC834x SYS board specific routines
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/module.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/bootinfo.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc83xx.h>
+#include <asm/irq.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+
+#include "mpc83xx.h"
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+#endif
+
+#ifdef CONFIG_PCI
+extern int mpc83xx_pci2_busno;
+
+static int
+mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+        static char pci_irq_table[][4] =
+            /*
+             *      PCI IDSEL/INTPIN->INTLINE
+             *       A      B      C      D
+             */
+        {
+                {PIRQA, PIRQB, PIRQC, PIRQD},   /* idsel 0x11 */
+                {PIRQC, PIRQD, PIRQA, PIRQB},   /* idsel 0x12 */
+                {PIRQD, PIRQA, PIRQB, PIRQC},   /* idsel 0x13 */
+                {0, 0, 0, 0},
+                {PIRQA, PIRQB, PIRQC, PIRQD},   /* idsel 0x15 */
+                {PIRQD, PIRQA, PIRQB, PIRQC},   /* idsel 0x16 */
+                {PIRQC, PIRQD, PIRQA, PIRQB},   /* idsel 0x17 */
+                {PIRQB, PIRQC, PIRQD, PIRQA},   /* idsel 0x18 */
+                {0, 0, 0, 0},                   /* idsel 0x19 */
+                {0, 0, 0, 0},                   /* idsel 0x20 */
+        };
+
+        const long min_idsel = 0x11, max_idsel = 0x20, irqs_per_slot = 4;
+        return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static int
+mpc83xx_exclude_device(u_char bus, u_char devfn)
+{
+        if (bus == 0 && PCI_SLOT(devfn) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        if (mpc83xx_pci2_busno)
+                if (bus == (mpc83xx_pci2_busno) && PCI_SLOT(devfn) == 0)
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+        return PCIBIOS_SUCCESSFUL;
+}
+#endif /* CONFIG_PCI */
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init
+mpc834x_sys_setup_arch(void)
+{
+        struct device_node *np;
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc834x_sys_setup_arch()", 0);
+
+        np = of_find_node_by_type(NULL, "cpu");
+        if (np != 0) {
+                unsigned int *fp = (int *) get_property(np, "clock-frequency", NULL);
+                if (fp != 0)
+                        loops_per_jiffy = *fp / HZ;
+                else
+                        loops_per_jiffy = 50000000 / HZ;
+                of_node_put(np);
+        }
+
+#ifdef CONFIG_PCI
+        for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+                add_bridge(np);
+
+        ppc_md.pci_swizzle = common_swizzle;
+        ppc_md.pci_map_irq = mpc83xx_map_irq;
+        ppc_md.pci_exclude_device = mpc83xx_exclude_device;
+#endif
+
+#ifdef  CONFIG_ROOT_NFS
+                ROOT_DEV = Root_NFS;
+#else
+                ROOT_DEV = Root_HDA1;
+#endif
+}
+
+void __init
+mpc834x_sys_init_IRQ(void)
+{
+        u8 senses[8] = {
+                0,                      /* EXT 0 */
+                IRQ_SENSE_LEVEL,        /* EXT 1 */
+                IRQ_SENSE_LEVEL,        /* EXT 2 */
+                0,                      /* EXT 3 */
+#ifdef CONFIG_PCI
+                IRQ_SENSE_LEVEL,        /* EXT 4 */
+                IRQ_SENSE_LEVEL,        /* EXT 5 */
+                IRQ_SENSE_LEVEL,        /* EXT 6 */
+                IRQ_SENSE_LEVEL,        /* EXT 7 */
+#else
+                0,                      /* EXT 4 */
+                0,                      /* EXT 5 */
+                0,                      /* EXT 6 */
+                0,                      /* EXT 7 */
+#endif
+        };
+
+        ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8);
+
+        /* Initialize the default interrupt mapping priorities,
+         * in case the boot rom changed something on us.
+         */
+        ipic_set_default_priority();
+}
+
+#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
+extern ulong    ds1374_get_rtc_time(void);
+extern int      ds1374_set_rtc_time(ulong);
+
+static int __init
+mpc834x_rtc_hookup(void)
+{
+        struct timespec tv;
+
+        ppc_md.get_rtc_time = ds1374_get_rtc_time;
+        ppc_md.set_rtc_time = ds1374_set_rtc_time;
+
+        tv.tv_nsec = 0;
+        tv.tv_sec = (ppc_md.get_rtc_time)();
+        do_settimeofday(&tv);
+
+        return 0;
+}
+late_initcall(mpc834x_rtc_hookup);
+#endif
+
+static void
+mpc83xx_restart(char *cmd)
+{
+#define RST_OFFSET      0x00000900
+#define RST_PROT_REG    0x00000018
+#define RST_CTRL_REG    0x0000001c
+        __be32 __iomem *reg;
+
+        // map reset register space
+        reg = ioremap(get_immrbase() + 0x900, 0xff);
+
+        local_irq_disable();
+
+        /* enable software reset "RSTE" */
+        out_be32(reg + (RST_PROT_REG >> 2), 0x52535445);
+
+        /* set software hard reset */
+        out_be32(reg + (RST_CTRL_REG >> 2), 0x52535445);
+        for(;;);
+}
+
+static long __init
+mpc83xx_time_init(void)
+{
+#define SPCR_OFFSET     0x00000110
+#define SPCR_TBEN       0x00400000
+        __be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
+        __be32 tmp;
+
+        tmp = in_be32(spcr);
+        out_be32(spcr, tmp|SPCR_TBEN);
+
+        iounmap(spcr);
+
+        return 0;
+}
+void __init
+platform_init(void)
+{
+        /* setup the PowerPC module struct */
+        ppc_md.setup_arch = mpc834x_sys_setup_arch;
+
+        ppc_md.init_IRQ = mpc834x_sys_init_IRQ;
+        ppc_md.get_irq = ipic_get_irq;
+
+        ppc_md.restart = mpc83xx_restart;
+
+        ppc_md.time_init = mpc83xx_time_init;
+        ppc_md.set_rtc_time = NULL;
+        ppc_md.get_rtc_time = NULL;
+        ppc_md.calibrate_decr = generic_calibrate_decr;
+
+        ppc_md.progress = udbg_progress;
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc834x_sys_init(): exit", 0);
+
+        return;
+}
+
+
diff --git a/arch/powerpc/platforms/83xx/mpc834x_sys.h b/arch/powerpc/platforms/83xx/mpc834x_sys.h
new file mode 100644
index 000000000000..e4ca39f6a862
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc834x_sys.h
@@ -0,0 +1,23 @@
+/*
+ * arch/powerppc/platforms/83xx/mpc834x_sys.h
+ *
+ * MPC834X SYS common board definitions
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MACH_MPC83XX_SYS_H__
+#define __MACH_MPC83XX_SYS_H__
+
+#define PIRQA   MPC83xx_IRQ_EXT4
+#define PIRQB   MPC83xx_IRQ_EXT5
+#define PIRQC   MPC83xx_IRQ_EXT6
+#define PIRQD   MPC83xx_IRQ_EXT7
+
+#endif                /* __MACH_MPC83XX_SYS_H__ */
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
new file mode 100644
index 000000000000..ce9e66abef24
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -0,0 +1,14 @@
+#ifndef __MPC83XX_H__
+#define __MPC83XX_H__
+
+#include <linux/init.h>
+#include <linux/device.h>
+
+/*
+ * Declaration for the various functions exported by the
+ * mpc83xx_* files. Mostly for use by mpc83xx_setup
+ */
+
+extern int add_bridge(struct device_node *dev);
+
+#endif /* __MPC83XX_H__ */
diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c
new file mode 100644
index 000000000000..469cdacc5bd4
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/pci.c
@@ -0,0 +1,99 @@
+/*
+ * FSL SoC setup code
+ *
+ * Maintained by Kumar Gala (see MAINTAINERS for contact information)
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/pci-bridge.h>
+#include <asm/prom.h>
+#include <sysdev/fsl_soc.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+int mpc83xx_pci2_busno;
+
+#ifdef CONFIG_PCI
+int __init add_bridge(struct device_node *dev)
+{
+        int len;
+        struct pci_controller *hose;
+        struct resource rsrc;
+        int *bus_range;
+        int primary = 1, has_address = 0;
+        phys_addr_t immr = get_immrbase();
+
+        DBG("Adding PCI host bridge %s\n", dev->full_name);
+
+        /* Fetch host bridge registers address */
+        has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
+
+        /* Get bus range if any */
+        bus_range = (int *) get_property(dev, "bus-range", &len);
+        if (bus_range == NULL || len < 2 * sizeof(int)) {
+                printk(KERN_WARNING "Can't get bus-range for %s, assume"
+                       " bus 0\n", dev->full_name);
+        }
+
+        hose = pcibios_alloc_controller();
+        if (!hose)
+                return -ENOMEM;
+        hose->arch_data = dev;
+        hose->set_cfg_type = 1;
+
+        hose->first_busno = bus_range ? bus_range[0] : 0;
+        hose->last_busno = bus_range ? bus_range[1] : 0xff;
+
+        /* MPC83xx supports up to two host controllers one at 0x8500 from immrbar
+         * the other at 0x8600, we consider the 0x8500 the primary controller
+         */
+        /* PCI 1 */
+        if ((rsrc.start & 0xfffff) == 0x8500) {
+                setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304);
+        }
+        /* PCI 2*/
+        if ((rsrc.start & 0xfffff) == 0x8600) {
+                setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384);
+                primary = 0;
+                hose->bus_offset = hose->first_busno;
+                mpc83xx_pci2_busno = hose->first_busno;
+        }
+
+        printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%08lx. "
+               "Firmware bus number: %d->%d\n",
+                rsrc.start, hose->first_busno, hose->last_busno);
+
+        DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
+                hose, hose->cfg_addr, hose->cfg_data);
+
+        /* Interpret the "ranges" property */
+        /* This also maps the I/O region and sets isa_io/mem_base */
+        pci_process_bridge_OF_ranges(hose, dev, primary);
+
+        return 0;
+}
+
+#endif