diff options
author | Kim Phillips <kim.phillips@freescale.com> | 2007-11-05 13:15:51 -0500 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2007-11-19 23:14:48 -0500 |
commit | 29a50a8bd04ce88efe530fad4d0e21d045c0f25a (patch) | |
tree | c19b8a37ed0c3eb9d5b2701c9db7dc2ad36a0b86 /arch/powerpc/platforms/83xx | |
parent | 34be4561cd47bab1cd5796ea355dd373264da288 (diff) |
[POWERPC] 83xx: Handle mpc8360 rev. 2.1 RGMII timing erratum
If on a rev. 2.1, adjust UCC clock and data timing characteristics
as specified in the rev.2.1 erratum #2.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/platforms/83xx')
-rw-r--r-- | arch/powerpc/platforms/83xx/mpc836x_mds.c | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c index 0f3855c95ff5..0a722601a2f0 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c | |||
@@ -96,14 +96,39 @@ static void __init mpc836x_mds_setup_arch(void) | |||
96 | 96 | ||
97 | if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) | 97 | if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) |
98 | != NULL){ | 98 | != NULL){ |
99 | uint svid; | ||
100 | |||
99 | /* Reset the Ethernet PHY */ | 101 | /* Reset the Ethernet PHY */ |
100 | bcsr_regs[9] &= ~0x20; | 102 | #define BCSR9_GETHRST 0x20 |
103 | clrbits8(&bcsr_regs[9], BCSR9_GETHRST); | ||
101 | udelay(1000); | 104 | udelay(1000); |
102 | bcsr_regs[9] |= 0x20; | 105 | setbits8(&bcsr_regs[9], BCSR9_GETHRST); |
106 | |||
107 | /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ | ||
108 | svid = mfspr(SPRN_SVR); | ||
109 | if (svid == 0x80480021) { | ||
110 | void __iomem *immap; | ||
111 | |||
112 | immap = ioremap(get_immrbase() + 0x14a8, 8); | ||
113 | |||
114 | /* | ||
115 | * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) | ||
116 | * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) | ||
117 | */ | ||
118 | setbits32(immap, 0x0c003000); | ||
119 | |||
120 | /* | ||
121 | * IMMR + 0x14AC[20:27] = 10101010 | ||
122 | * (data delay for both UCC's) | ||
123 | */ | ||
124 | clrsetbits_be32(immap + 4, 0xff0, 0xaa0); | ||
125 | |||
126 | iounmap(immap); | ||
127 | } | ||
128 | |||
103 | iounmap(bcsr_regs); | 129 | iounmap(bcsr_regs); |
104 | of_node_put(np); | 130 | of_node_put(np); |
105 | } | 131 | } |
106 | |||
107 | #endif /* CONFIG_QUICC_ENGINE */ | 132 | #endif /* CONFIG_QUICC_ENGINE */ |
108 | } | 133 | } |
109 | 134 | ||