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authorJoel Stanley <joel@jms.id.au>2014-07-08 02:38:21 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-07-10 22:55:07 -0400
commit4d9690dd56b0d18f2af8a9d4a279cb205aae3345 (patch)
treeba7cea5414444ccf79b27d3c1975bdbe18f14c27 /arch/powerpc/perf
parentf73128f4f680e8be68cda831f2710214559583cb (diff)
powerpc/perf: Add PPMU_ARCH_207S define
Instead of separate bits for every POWER8 PMU feature, have a single one for v2.07 of the architecture. This saves us adding a MMCR2 define for a future patch. Cc: stable@vger.kernel.org Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/perf')
-rw-r--r--arch/powerpc/perf/core-book3s.c6
-rw-r--r--arch/powerpc/perf/power8-pmu.c2
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 4520c9356b54..a2ff1bda706a 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -485,7 +485,7 @@ static bool is_ebb_event(struct perf_event *event)
485 * check that the PMU supports EBB, meaning those that don't can still 485 * check that the PMU supports EBB, meaning those that don't can still
486 * use bit 63 of the event code for something else if they wish. 486 * use bit 63 of the event code for something else if they wish.
487 */ 487 */
488 return (ppmu->flags & PPMU_EBB) && 488 return (ppmu->flags & PPMU_ARCH_207S) &&
489 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 489 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
490} 490}
491 491
@@ -777,7 +777,7 @@ void perf_event_print_debug(void)
777 if (ppmu->flags & PPMU_HAS_SIER) 777 if (ppmu->flags & PPMU_HAS_SIER)
778 sier = mfspr(SPRN_SIER); 778 sier = mfspr(SPRN_SIER);
779 779
780 if (ppmu->flags & PPMU_EBB) { 780 if (ppmu->flags & PPMU_ARCH_207S) {
781 pr_info("MMCR2: %016lx EBBHR: %016lx\n", 781 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
782 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 782 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
783 pr_info("EBBRR: %016lx BESCR: %016lx\n", 783 pr_info("EBBRR: %016lx BESCR: %016lx\n",
@@ -1696,7 +1696,7 @@ static int power_pmu_event_init(struct perf_event *event)
1696 1696
1697 if (has_branch_stack(event)) { 1697 if (has_branch_stack(event)) {
1698 /* PMU has BHRB enabled */ 1698 /* PMU has BHRB enabled */
1699 if (!(ppmu->flags & PPMU_BHRB)) 1699 if (!(ppmu->flags & PPMU_ARCH_207S))
1700 return -EOPNOTSUPP; 1700 return -EOPNOTSUPP;
1701 } 1701 }
1702 1702
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index fe2763b6e039..639cd9156585 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -792,7 +792,7 @@ static struct power_pmu power8_pmu = {
792 .get_constraint = power8_get_constraint, 792 .get_constraint = power8_get_constraint,
793 .get_alternatives = power8_get_alternatives, 793 .get_alternatives = power8_get_alternatives,
794 .disable_pmc = power8_disable_pmc, 794 .disable_pmc = power8_disable_pmc,
795 .flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB, 795 .flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_ARCH_207S,
796 .n_generic = ARRAY_SIZE(power8_generic_events), 796 .n_generic = ARRAY_SIZE(power8_generic_events),
797 .generic_events = power8_generic_events, 797 .generic_events = power8_generic_events,
798 .cache_events = &power8_cache_events, 798 .cache_events = &power8_cache_events,