diff options
author | Octavian Purdila <opurdila@ixiacom.com> | 2009-02-23 21:09:58 -0500 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-03-11 02:10:16 -0400 |
commit | f8ff96db9be035a01065a8528c016d125945479a (patch) | |
tree | 101320f0691ddbf65722579c61b1dc99f19e2c73 /arch/powerpc/oprofile | |
parent | 8f748aae4b5eda6a6ec3ab3554e7e19c7702ccc2 (diff) |
powerpc/oprofile: G4 oprofile has variable number of counters
For ppc750 processors which use 4 performance counters instead of the
6 G4 uses but otherwise is compatible with G4.
Signed-off-by: Octavian Purdila <opurdila@ixiacom.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/oprofile')
-rw-r--r-- | arch/powerpc/oprofile/op_model_7450.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/arch/powerpc/oprofile/op_model_7450.c b/arch/powerpc/oprofile/op_model_7450.c index cc599eb8768b..f8d36f940e88 100644 --- a/arch/powerpc/oprofile/op_model_7450.c +++ b/arch/powerpc/oprofile/op_model_7450.c | |||
@@ -29,7 +29,7 @@ | |||
29 | static unsigned long reset_value[OP_MAX_COUNTER]; | 29 | static unsigned long reset_value[OP_MAX_COUNTER]; |
30 | 30 | ||
31 | static int oprofile_running; | 31 | static int oprofile_running; |
32 | static u32 mmcr0_val, mmcr1_val, mmcr2_val; | 32 | static u32 mmcr0_val, mmcr1_val, mmcr2_val, num_pmcs; |
33 | 33 | ||
34 | #define MMCR0_PMC1_SHIFT 6 | 34 | #define MMCR0_PMC1_SHIFT 6 |
35 | #define MMCR0_PMC2_SHIFT 0 | 35 | #define MMCR0_PMC2_SHIFT 0 |
@@ -88,13 +88,12 @@ static int fsl7450_cpu_setup(struct op_counter_config *ctr) | |||
88 | 88 | ||
89 | mtspr(SPRN_MMCR0, mmcr0_val); | 89 | mtspr(SPRN_MMCR0, mmcr0_val); |
90 | mtspr(SPRN_MMCR1, mmcr1_val); | 90 | mtspr(SPRN_MMCR1, mmcr1_val); |
91 | mtspr(SPRN_MMCR2, mmcr2_val); | 91 | if (num_pmcs > 4) |
92 | mtspr(SPRN_MMCR2, mmcr2_val); | ||
92 | 93 | ||
93 | return 0; | 94 | return 0; |
94 | } | 95 | } |
95 | 96 | ||
96 | #define NUM_CTRS 6 | ||
97 | |||
98 | /* Configures the global settings for the countes on all CPUs. */ | 97 | /* Configures the global settings for the countes on all CPUs. */ |
99 | static int fsl7450_reg_setup(struct op_counter_config *ctr, | 98 | static int fsl7450_reg_setup(struct op_counter_config *ctr, |
100 | struct op_system_config *sys, | 99 | struct op_system_config *sys, |
@@ -102,12 +101,13 @@ static int fsl7450_reg_setup(struct op_counter_config *ctr, | |||
102 | { | 101 | { |
103 | int i; | 102 | int i; |
104 | 103 | ||
104 | num_pmcs = num_ctrs; | ||
105 | /* Our counters count up, and "count" refers to | 105 | /* Our counters count up, and "count" refers to |
106 | * how much before the next interrupt, and we interrupt | 106 | * how much before the next interrupt, and we interrupt |
107 | * on overflow. So we calculate the starting value | 107 | * on overflow. So we calculate the starting value |
108 | * which will give us "count" until overflow. | 108 | * which will give us "count" until overflow. |
109 | * Then we set the events on the enabled counters */ | 109 | * Then we set the events on the enabled counters */ |
110 | for (i = 0; i < NUM_CTRS; ++i) | 110 | for (i = 0; i < num_ctrs; ++i) |
111 | reset_value[i] = 0x80000000UL - ctr[i].count; | 111 | reset_value[i] = 0x80000000UL - ctr[i].count; |
112 | 112 | ||
113 | /* Set events for Counters 1 & 2 */ | 113 | /* Set events for Counters 1 & 2 */ |
@@ -123,9 +123,10 @@ static int fsl7450_reg_setup(struct op_counter_config *ctr, | |||
123 | 123 | ||
124 | /* Set events for Counters 3-6 */ | 124 | /* Set events for Counters 3-6 */ |
125 | mmcr1_val = mmcr1_event3(ctr[2].event) | 125 | mmcr1_val = mmcr1_event3(ctr[2].event) |
126 | | mmcr1_event4(ctr[3].event) | 126 | | mmcr1_event4(ctr[3].event); |
127 | | mmcr1_event5(ctr[4].event) | 127 | if (num_ctrs > 4) |
128 | | mmcr1_event6(ctr[5].event); | 128 | mmcr1_val |= mmcr1_event5(ctr[4].event) |
129 | | mmcr1_event6(ctr[5].event); | ||
129 | 130 | ||
130 | mmcr2_val = 0; | 131 | mmcr2_val = 0; |
131 | 132 | ||
@@ -139,7 +140,7 @@ static int fsl7450_start(struct op_counter_config *ctr) | |||
139 | 140 | ||
140 | mtmsr(mfmsr() | MSR_PMM); | 141 | mtmsr(mfmsr() | MSR_PMM); |
141 | 142 | ||
142 | for (i = 0; i < NUM_CTRS; ++i) { | 143 | for (i = 0; i < num_pmcs; ++i) { |
143 | if (ctr[i].enabled) | 144 | if (ctr[i].enabled) |
144 | classic_ctr_write(i, reset_value[i]); | 145 | classic_ctr_write(i, reset_value[i]); |
145 | else | 146 | else |
@@ -184,7 +185,7 @@ static void fsl7450_handle_interrupt(struct pt_regs *regs, | |||
184 | pc = mfspr(SPRN_SIAR); | 185 | pc = mfspr(SPRN_SIAR); |
185 | is_kernel = is_kernel_addr(pc); | 186 | is_kernel = is_kernel_addr(pc); |
186 | 187 | ||
187 | for (i = 0; i < NUM_CTRS; ++i) { | 188 | for (i = 0; i < num_pmcs; ++i) { |
188 | val = classic_ctr_read(i); | 189 | val = classic_ctr_read(i); |
189 | if (val < 0) { | 190 | if (val < 0) { |
190 | if (oprofile_running && ctr[i].enabled) { | 191 | if (oprofile_running && ctr[i].enabled) { |