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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-08-18 00:23:51 -0400
committerPaul Mackerras <paulus@samba.org>2008-08-20 02:34:58 -0400
commitb950bdd0fc247d0ab4aea88d46e8cced3eac949e (patch)
treedaea275d042511774a6abd558d963e1199aedb65 /arch/powerpc/oprofile
parent41eba0ad0033967eda346dd833194e96fdf5f405 (diff)
powerpc: Expose PMCs & cache topology in sysfs on 32-bit
The file arch/powerpc/kernel/sysfs.c is currently only compiled for 64-bit kernels. It contain code to register CPU sysdevs in sysfs and add various properties such as cache topology and raw access by root to performance monitor counters (PMCs). A lot of that can be re-used as is on 32-bits. This makes the file be built for both, with appropriate ifdef'ing for the few bits that are really 64-bit specific, and adds some support for the raw PMCs for 75x and 74xx processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/oprofile')
-rw-r--r--arch/powerpc/oprofile/op_model_power4.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c
index 446a8bbb847b..3e3d91f536e0 100644
--- a/arch/powerpc/oprofile/op_model_power4.c
+++ b/arch/powerpc/oprofile/op_model_power4.c
@@ -64,7 +64,7 @@ static int power4_reg_setup(struct op_counter_config *ctr,
64 return 0; 64 return 0;
65} 65}
66 66
67extern void ppc64_enable_pmcs(void); 67extern void ppc_enable_pmcs(void);
68 68
69/* 69/*
70 * Older CPUs require the MMCRA sample bit to be always set, but newer 70 * Older CPUs require the MMCRA sample bit to be always set, but newer
@@ -91,7 +91,7 @@ static int power4_cpu_setup(struct op_counter_config *ctr)
91 unsigned int mmcr0 = mmcr0_val; 91 unsigned int mmcr0 = mmcr0_val;
92 unsigned long mmcra = mmcra_val; 92 unsigned long mmcra = mmcra_val;
93 93
94 ppc64_enable_pmcs(); 94 ppc_enable_pmcs();
95 95
96 /* set the freeze bit */ 96 /* set the freeze bit */
97 mmcr0 |= MMCR0_FC; 97 mmcr0 |= MMCR0_FC;