Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc updates from Benjamin Herrenschmidt:
 "The bulk of this is LE updates.  One should now be able to build an LE
  kernel and even run some things in it.

  I'm still sitting on a handful of patches to enable the new ABI that I
  *might* still send this merge window around, but due to the
  incertainty (they are pretty fresh) I want to keep them separate.

  Other notable changes are some infrastructure bits to better handle
  PCI pass-through under KVM, some bits and pieces added to the new
  PowerNV platform support such as access to the CPU SCOM bus via sysfs,
  and support for EEH error handling on PHB3 (Power8 PCIe).

  We also grew arch_get_random_long() for both pseries and powernv when
  running on P7+ and P8, exploiting the HW rng.

  And finally various embedded updates from freescale"

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (154 commits)
  powerpc: Fix fatal SLB miss when restoring PPR
  powerpc/powernv: Reserve the correct PE number
  powerpc/powernv: Add PE to its own PELTV
  powerpc/powernv: Add support for indirect XSCOM via debugfs
  powerpc/scom: Improve debugfs interface
  powerpc/scom: Enable 64-bit addresses
  powerpc/boot: Properly handle the base "of" boot wrapper
  powerpc/bpf: Support MOD operation
  powerpc/bpf: Fix DIVWU instruction opcode
  of: Move definition of of_find_next_cache_node into common code.
  powerpc: Remove big endianness assumption in of_find_next_cache_node
  powerpc/tm: Remove interrupt disable in __switch_to()
  powerpc: word-at-a-time optimization for 64-bit Little Endian
  powerpc/bpf: BPF JIT compiler for 64-bit Little Endian
  powerpc: Only save/restore SDR1 if in hypervisor mode
  powerpc/pmu: Fix ADB_PMU_LED_IDE dependencies
  powerpc/nvram: Fix endian issue when using the partition length
  powerpc/nvram: Fix endian issue when reading the NVRAM size
  powerpc/nvram: Scan partitions only once
  powerpc/mpc512x: remove unnecessary #if
  ...

3 files changed, 41 insertions, 16 deletions

diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index 8a5dfaf5c6b7..9aee27c582dc 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -39,6 +39,7 @@
 #define r_X             5
 #define r_addr          6
 #define r_scratch1      7
+#define r_scratch2      8
 #define r_D             14
 #define r_HL            15
 #define r_M             16
@@ -92,6 +93,8 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
                                      ___PPC_RA(base) | IMM_L(i))
 #define PPC_LHZ(r, base, i)     EMIT(PPC_INST_LHZ | ___PPC_RT(r) |            \
                                      ___PPC_RA(base) | IMM_L(i))
+#define PPC_LHBRX(r, base, b)   EMIT(PPC_INST_LHBRX | ___PPC_RT(r) |          \
+                                     ___PPC_RA(base) | ___PPC_RB(b))
 /* Convenience helpers for the above with 'far' offsets: */
 #define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i);     \
                 else {  PPC_ADDIS(r, base, IMM_HA(i));                        \
@@ -186,6 +189,14 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
                                 PPC_ORI(d, d, (uintptr_t)(i) & 0xffff);       \
                 } } while (0);
 
+#define PPC_LHBRX_OFFS(r, base, i) \
+                do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0)
+#ifdef __LITTLE_ENDIAN__
+#define PPC_NTOHS_OFFS(r, base, i)      PPC_LHBRX_OFFS(r, base, i)
+#else
+#define PPC_NTOHS_OFFS(r, base, i)      PPC_LHZ_OFFS(r, base, i)
+#endif
+
 static inline bool is_nearbranch(int offset)
 {
         return (offset < 32768) && (offset >= -32768);
diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S
index 7d3a3b5619a2..e76eba74d9da 100644
--- a/arch/powerpc/net/bpf_jit_64.S
+++ b/arch/powerpc/net/bpf_jit_64.S
@@ -43,8 +43,11 @@ sk_load_word_positive_offset:
         cmpd    r_scratch1, r_addr
         blt     bpf_slow_path_word
         /* Nope, just hitting the header.  cr0 here is eq or gt! */
+#ifdef __LITTLE_ENDIAN__
+        lwbrx   r_A, r_D, r_addr
+#else
         lwzx    r_A, r_D, r_addr
-        /* When big endian we don't need to byteswap. */
+#endif
         blr     /* Return success, cr0 != LT */
 
         .globl  sk_load_half
@@ -56,7 +59,11 @@ sk_load_half_positive_offset:
         subi    r_scratch1, r_HL, 2
         cmpd    r_scratch1, r_addr
         blt     bpf_slow_path_half
+#ifdef __LITTLE_ENDIAN__
+        lhbrx   r_A, r_D, r_addr
+#else
         lhzx    r_A, r_D, r_addr
+#endif
         blr
 
         .globl  sk_load_byte
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index 2345bdb4d917..ac3c2a10dafd 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -17,14 +17,8 @@
 
 #include "bpf_jit.h"
 
-#ifndef __BIG_ENDIAN
-/* There are endianness assumptions herein. */
-#error "Little-endian PPC not supported in BPF compiler"
-#endif
-
 int bpf_jit_enable __read_mostly;
 
-
 static inline void bpf_flush_icache(void *start, void *end)
 {
         smp_wmb();
@@ -193,6 +187,26 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                                 PPC_MUL(r_A, r_A, r_scratch1);
                         }
                         break;
+                case BPF_S_ALU_MOD_X: /* A %= X; */
+                        ctx->seen |= SEEN_XREG;
+                        PPC_CMPWI(r_X, 0);
+                        if (ctx->pc_ret0 != -1) {
+                                PPC_BCC(COND_EQ, addrs[ctx->pc_ret0]);
+                        } else {
+                                PPC_BCC_SHORT(COND_NE, (ctx->idx*4)+12);
+                                PPC_LI(r_ret, 0);
+                                PPC_JMP(exit_addr);
+                        }
+                        PPC_DIVWU(r_scratch1, r_A, r_X);
+                        PPC_MUL(r_scratch1, r_X, r_scratch1);
+                        PPC_SUB(r_A, r_A, r_scratch1);
+                        break;
+                case BPF_S_ALU_MOD_K: /* A %= K; */
+                        PPC_LI32(r_scratch2, K);
+                        PPC_DIVWU(r_scratch1, r_A, r_scratch2);
+                        PPC_MUL(r_scratch1, r_scratch2, r_scratch1);
+                        PPC_SUB(r_A, r_A, r_scratch1);
+                        break;
                 case BPF_S_ALU_DIV_X: /* A /= X; */
                         ctx->seen |= SEEN_XREG;
                         PPC_CMPWI(r_X, 0);
@@ -346,18 +360,11 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                         break;
 
                         /*** Ancillary info loads ***/
-
-                        /* None of the BPF_S_ANC* codes appear to be passed by
-                         * sk_chk_filter().  The interpreter and the x86 BPF
-                         * compiler implement them so we do too -- they may be
-                         * planted in future.
-                         */
                 case BPF_S_ANC_PROTOCOL: /* A = ntohs(skb->protocol); */
                         BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
                                                   protocol) != 2);
-                        PPC_LHZ_OFFS(r_A, r_skb, offsetof(struct sk_buff,
-                                                          protocol));
-                        /* ntohs is a NOP with BE loads. */
+                        PPC_NTOHS_OFFS(r_A, r_skb, offsetof(struct sk_buff,
+                                                            protocol));
                         break;
                 case BPF_S_ANC_IFINDEX:
                         PPC_LD_OFFS(r_scratch1, r_skb, offsetof(struct sk_buff,