powerpc/mm: Free up _PAGE_COHERENCE for numa fault use later

Set  memory coherence always on hash64 config. If
a platform cannot have memory coherence always set they
can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU
like in lpar. So we dont' really need a separate bit
for tracking _PAGE_COHERENCE.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

4 files changed, 25 insertions, 7 deletions

diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index d3cbda62857b..1136d26a95ae 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -148,7 +148,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
         andc    r0,r30,r0               /* r0 = pte & ~r0 */
         rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-        ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
+        /*
+         * Always add "C" bit for perf. Memory coherence is always enabled
+         */
+        ori     r3,r3,HPTE_R_C | HPTE_R_M
 
         /* We eventually do the icache sync here (maybe inline that
          * code rather than call a C function...) 
@@ -457,7 +460,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
         andc    r0,r3,r0                /* r0 = pte & ~r0 */
         rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-        ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
+        /*
+         * Always add "C" bit for perf. Memory coherence is always enabled
+         */
+        ori     r3,r3,HPTE_R_C | HPTE_R_M
 
         /* We eventually do the icache sync here (maybe inline that
          * code rather than call a C function...)
@@ -795,7 +801,10 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         and     r0,r0,r4                /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
         andc    r0,r30,r0               /* r0 = pte & ~r0 */
         rlwimi  r3,r0,32-1,31,31        /* Insert result into PP lsb */
-        ori     r3,r3,HPTE_R_C          /* Always add "C" bit for perf. */
+        /*
+         * Always add "C" bit for perf. Memory coherence is always enabled
+         */
+        ori     r3,r3,HPTE_R_C | HPTE_R_M
 
         /* We eventually do the icache sync here (maybe inline that
          * code rather than call a C function...)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 6176b3cdf579..de6881259aef 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -169,9 +169,10 @@ static unsigned long htab_convert_pte_flags(unsigned long pteflags)
         if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
                                          (pteflags & _PAGE_DIRTY)))
                 rflags |= 1;
-
-        /* Always add C */
-        return rflags | HPTE_R_C;
+        /*
+         * Always add "C" bit for perf. Memory coherence is always enabled
+         */
+        return rflags | HPTE_R_C | HPTE_R_M;
 }
 
 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
diff --git a/arch/powerpc/mm/hugepage-hash64.c b/arch/powerpc/mm/hugepage-hash64.c
index 34de9e0cdc34..826893fcb3a7 100644
--- a/arch/powerpc/mm/hugepage-hash64.c
+++ b/arch/powerpc/mm/hugepage-hash64.c
@@ -127,7 +127,11 @@ repeat:
 
                 /* Add in WIMG bits */
                 rflags |= (new_pmd & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
-                                      _PAGE_COHERENT | _PAGE_GUARDED));
+                                      _PAGE_GUARDED));
+                /*
+                 * enable the memory coherence always
+                 */
+                rflags |= HPTE_R_M;
 
                 /* Insert into the hash table, primary slot */
                 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, 0,
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index 0b7fb6761015..a5bcf9301196 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -99,6 +99,10 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
                 /* Add in WIMG bits */
                 rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
                                       _PAGE_COHERENT | _PAGE_GUARDED));
+                /*
+                 * enable the memory coherence always
+                 */
+                rflags |= HPTE_R_M;
 
                 slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0,
                                              mmu_psize, ssize);