powerpc: Use new CPU feature bit to select 2.06 tlbie

This removes MMU_FTR_TLBIE_206 as we can now use CPU_FTR_HVMODE_206.  It
also changes the logic to select which tlbie to use to be based on this
new CPU feature bit.

This also duplicates the ASM_FTR_IF/SET/CLR defines for CPU features
(copied from MMU features).

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 4 insertions, 6 deletions

diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index c23eef2b81a6..dfd764896db0 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -50,9 +50,8 @@ static inline void __tlbie(unsigned long va, int psize, int ssize)
         case MMU_PAGE_4K:
                 va &= ~0xffful;
                 va |= ssize << 8;
-                asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0),
-                                               %2)
-                             : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+                asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
+                             : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206)
                              : "memory");
                 break;
         default:
@@ -61,9 +60,8 @@ static inline void __tlbie(unsigned long va, int psize, int ssize)
                 va |= penc << 12;
                 va |= ssize << 8;
                 va |= 1; /* L */
-                asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0),
-                                               %2)
-                             : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+                asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
+                             : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206)
                              : "memory");
                 break;
         }