Merge commit 'jwb/jwb-next'

5 files changed, 38 insertions, 10 deletions

diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 953fb919eb06..98052ac96580 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -27,6 +27,7 @@
 #include <asm/mmu.h>
 #include <asm/system.h>
 #include <asm/page.h>
+#include <asm/cacheflush.h>
 
 #include "mmu_decl.h"
 
@@ -37,11 +38,35 @@ unsigned int tlb_44x_index; /* = 0 */
 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
 int icache_44x_need_flush;
 
+static void __init ppc44x_update_tlb_hwater(void)
+{
+        extern unsigned int tlb_44x_patch_hwater_D[];
+        extern unsigned int tlb_44x_patch_hwater_I[];
+
+        /* The TLB miss handlers hard codes the watermark in a cmpli
+         * instruction to improve performances rather than loading it
+         * from the global variable. Thus, we patch the instructions
+         * in the 2 TLB miss handlers when updating the value
+         */
+        tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) |
+                tlb_44x_hwater;
+        flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0],
+                           (unsigned long)&tlb_44x_patch_hwater_D[1]);
+        tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) |
+                tlb_44x_hwater;
+        flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0],
+                           (unsigned long)&tlb_44x_patch_hwater_I[1]);
+}
+
 /*
  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
  */
 static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
 {
+        unsigned int entry = tlb_44x_hwater--;
+
+        ppc44x_update_tlb_hwater();
+
         __asm__ __volatile__(
                 "tlbwe  %2,%3,%4\n"
                 "tlbwe  %1,%3,%5\n"
@@ -50,7 +75,7 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
         : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
           "r" (phys),
           "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
-          "r" (tlb_44x_hwater--), /* slot for this TLB entry */
+          "r" (entry),
           "i" (PPC44x_TLB_PAGEID),
           "i" (PPC44x_TLB_XLAT),
           "i" (PPC44x_TLB_ATTRIB));
@@ -58,6 +83,8 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
 
 void __init MMU_init_hw(void)
 {
+        ppc44x_update_tlb_hwater();
+
         flush_instruction_cache();
 }
 
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 7b2510799266..1707d00331fc 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -306,7 +306,8 @@ good_area:
                                         flush_dcache_icache_page(page);
                                         set_bit(PG_arch_1, &page->flags);
                                 }
-                                pte_update(ptep, 0, _PAGE_HWEXEC);
+                                pte_update(ptep, 0, _PAGE_HWEXEC |
+                                           _PAGE_ACCESSED);
                                 _tlbie(address, mm->context.id);
                                 pte_unmap_unlock(ptep, ptl);
                                 up_read(&mm->mmap_sem);
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 45418590b6a9..388ceda632f3 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -57,8 +57,8 @@
 
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 
-unsigned long total_memory;
-unsigned long total_lowmem;
+phys_addr_t total_memory;
+phys_addr_t total_lowmem;
 
 phys_addr_t memstart_addr = (phys_addr_t)~0ull;
 EXPORT_SYMBOL(memstart_addr);
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 776ba6ad5e1e..1ca2235f0965 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -330,7 +330,7 @@ static int __init mark_nonram_nosave(void)
 void __init paging_init(void)
 {
         unsigned long total_ram = lmb_phys_mem_size();
-        unsigned long top_of_ram = lmb_end_of_DRAM();
+        phys_addr_t top_of_ram = lmb_end_of_DRAM();
         unsigned long max_zone_pfns[MAX_NR_ZONES];
 
 #ifdef CONFIG_PPC32
@@ -349,10 +349,10 @@ void __init paging_init(void)
         kmap_prot = PAGE_KERNEL;
 #endif /* CONFIG_HIGHMEM */
 
-        printk(KERN_DEBUG "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
-               top_of_ram, total_ram);
+        printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%lx\n",
+               (u64)top_of_ram, total_ram);
         printk(KERN_DEBUG "Memory hole size: %ldMB\n",
-               (top_of_ram - total_ram) >> 20);
+               (long int)((top_of_ram - total_ram) >> 20));
         memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
 #ifdef CONFIG_HIGHMEM
         max_zone_pfns[ZONE_DMA] = lowmem_end_addr >> PAGE_SHIFT;
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 46585b7bb194..fab3cfad4099 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -49,8 +49,8 @@ extern unsigned int num_tlbcam_entries;
 extern unsigned long ioremap_bot;
 extern unsigned long __max_low_memory;
 extern phys_addr_t __initial_memory_limit_addr;
-extern unsigned long total_memory;
-extern unsigned long total_lowmem;
+extern phys_addr_t total_memory;
+extern phys_addr_t total_lowmem;
 extern phys_addr_t memstart_addr;
 extern phys_addr_t lowmem_end_addr;