memblock: Remove rmo_size, burry it in arch/powerpc where it belongs

The RMA (RMO is a misnomer) is a concept specific to ppc64 (in fact
server ppc64 though I hijack it on embedded ppc64 for similar purposes)
and represents the area of memory that can be accessed in real mode
(aka with MMU off), or on embedded, from the exception vectors (which
is bolted in the TLB) which pretty much boils down to the same thing.

We take that out of the generic MEMBLOCK data structure and move it into
arch/powerpc where it belongs, renaming it to "RMA" while at it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

8 files changed, 101 insertions, 2 deletions

diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c
index 58969b51f454..5810967511d4 100644
--- a/arch/powerpc/mm/40x_mmu.c
+++ b/arch/powerpc/mm/40x_mmu.c
@@ -141,7 +141,19 @@ unsigned long __init mmu_mapin_ram(unsigned long top)
          * coverage with normal-sized pages (or other reasons) do not
          * attempt to allocate outside the allowed range.
          */
-        memblock_set_current_limit(memstart_addr + mapped);
+        memblock_set_current_limit(mapped);
 
         return mapped;
 }
+
+void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+                                phys_addr_t first_memblock_size)
+{
+        /* We don't currently support the first MEMBLOCK not mapping 0
+         * physical on those processors
+         */
+        BUG_ON(first_memblock_base != 0);
+
+        /* 40x can only access 16MB at the moment (see head_40x.S) */
+        memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
+}
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index d8c6efb32bc6..024acab588fd 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -24,6 +24,8 @@
  */
 
 #include <linux/init.h>
+#include <linux/memblock.h>
+
 #include <asm/mmu.h>
 #include <asm/system.h>
 #include <asm/page.h>
@@ -213,6 +215,18 @@ unsigned long __init mmu_mapin_ram(unsigned long top)
         return total_lowmem;
 }
 
+void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+                                phys_addr_t first_memblock_size)
+{
+        /* We don't currently support the first MEMBLOCK not mapping 0
+         * physical on those processors
+         */
+        BUG_ON(first_memblock_base != 0);
+
+        /* 44x has a 256M TLB entry pinned at boot */
+        memblock_set_current_limit(min_t(u64, first_memblock_size, PPC_PIN_SIZE));
+}
+
 #ifdef CONFIG_SMP
 void __cpuinit mmu_init_secondary(int cpu)
 {
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index e525f862d759..0be8fe24c54e 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -215,3 +215,12 @@ void __init adjust_total_lowmem(void)
 
         memblock_set_current_limit(memstart_addr + __max_low_memory);
 }
+
+void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+                                phys_addr_t first_memblock_size)
+{
+        phys_addr_t limit = first_memblock_base + first_memblock_size;
+
+        /* 64M mapped initially according to head_fsl_booke.S */
+        memblock_set_current_limit(min_t(u64, limit, 0x04000000));
+}
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index b05890e23813..83f534d862db 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -649,7 +649,7 @@ static void __init htab_initialize(void)
 #ifdef CONFIG_DEBUG_PAGEALLOC
         linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
         linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
-                                                    1, memblock.rmo_size));
+                                                    1, ppc64_rma_size));
         memset(linear_map_hash_slots, 0, linear_map_hash_count);
 #endif /* CONFIG_DEBUG_PAGEALLOC */
 
@@ -1248,3 +1248,23 @@ void kernel_map_pages(struct page *page, int numpages, int enable)
         local_irq_restore(flags);
 }
 #endif /* CONFIG_DEBUG_PAGEALLOC */
+
+void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+                                phys_addr_t first_memblock_size)
+{
+        /* We don't currently support the first MEMBLOCK not mapping 0
+         * physical on those processors
+         */
+        BUG_ON(first_memblock_base != 0);
+
+        /* On LPAR systems, the first entry is our RMA region,
+         * non-LPAR 64-bit hash MMU systems don't have a limitation
+         * on real mode access, but using the first entry works well
+         * enough. We also clamp it to 1G to avoid some funky things
+         * such as RTAS bugs etc...
+         */
+        ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
+
+        /* Finally limit subsequent allocations */
+        memblock_set_current_limit(ppc64_rma_size);
+}
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 59b208b7ec6f..742da43b4ab6 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -237,3 +237,17 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 }
 #endif
 
+
+#ifdef CONFIG_8xx /* No 8xx specific .c file to put that in ... */
+void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+                                phys_addr_t first_memblock_size)
+{
+        /* We don't currently support the first MEMBLOCK not mapping 0
+         * physical on those processors
+         */
+        BUG_ON(first_memblock_base != 0);
+
+        /* 8xx can only access 8MB at the moment */
+        memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
+}
+#endif /* CONFIG_8xx */
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index 71f1415e2472..9e081ffbf0f2 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -328,3 +328,4 @@ int __meminit vmemmap_populate(struct page *start_page,
         return 0;
 }
 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
+
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index 7d34e170e80f..11571e118831 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -271,3 +271,18 @@ void __init MMU_init_hw(void)
 
         if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
 }
+
+void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+                                phys_addr_t first_memblock_size)
+{
+        /* We don't currently support the first MEMBLOCK not mapping 0
+         * physical on those processors
+         */
+        BUG_ON(first_memblock_base != 0);
+
+        /* 601 can only access 16MB at the moment */
+        if (PVR_VER(mfspr(SPRN_PVR)) == 1)
+                memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01000000));
+        else /* Anything else has 256M mapped */
+                memblock_set_current_limit(min_t(u64, first_memblock_size, 0x10000000));
+}
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 7ba32e762990..a086ed562606 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -446,4 +446,18 @@ void __cpuinit early_init_mmu_secondary(void)
         __early_init_mmu(0);
 }
 
+void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+                                phys_addr_t first_memblock_size)
+{
+        /* On Embedded 64-bit, we adjust the RMA size to match
+         * the bolted TLB entry. We know for now that only 1G
+         * entries are supported though that may eventually
+         * change. We crop it to the size of the first MEMBLOCK to
+         * avoid going over total available memory just in case...
+         */
+        ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
+
+        /* Finally limit subsequent allocations */
+        memblock_set_current_limit(ppc64_memblock_base + ppc64_rma_size);
+}
 #endif /* CONFIG_PPC64 */