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authorTrent Piepho <tpiepho@freescale.com>2008-12-08 22:34:59 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-01-28 19:16:53 -0500
commitc8f3570b7e2dd070ba6da41f3ed4ffb4e1d296af (patch)
treee1f8a91bdc37a10583e1b987d5cecf91b9362a30 /arch/powerpc/mm
parentf88747e7f68866f2f82cef1363c5b8e7aa13b0a3 (diff)
powerpc/fsl-booke: Allow larger CAM sizes than 256 MB
The code that maps kernel low memory would only use page sizes up to 256 MB. On E500v2 pages up to 4 GB are supported. However, a page must be aligned to a multiple of the page's size. I.e. 256 MB pages must aligned to a 256 MB boundary. This was enforced by a requirement that the physical and virtual addresses of the start of lowmem be aligned to 256 MB. Clearly requiring 1GB or 4GB alignment to allow pages of that size isn't acceptable. To solve this, I simply have adjust_total_lowmem() take alignment into account when it decides what size pages to use. Give it PAGE_OFFSET = 0x7000_0000, PHYSICAL_START = 0x3000_0000, and 2GB of RAM, and it will map pages like this: PA 0x3000_0000 VA 0x7000_0000 Size 256 MB PA 0x4000_0000 VA 0x8000_0000 Size 1 GB PA 0x8000_0000 VA 0xC000_0000 Size 256 MB PA 0x9000_0000 VA 0xD000_0000 Size 256 MB PA 0xA000_0000 VA 0xE000_0000 Size 256 MB Because the lowmem mapping code now takes alignment into account, PHYSICAL_ALIGN can be lowered from 256 MB to 64 MB. Even lower might be possible. The lowmem code will work down to 4 kB but it's possible some of the boot code will fail before then. Poor alignment will force small pages to be used, which combined with the limited number of TLB1 pages available, will result in very little memory getting mapped. So alignments less than 64 MB probably aren't very useful anyway. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm')
-rw-r--r--arch/powerpc/mm/fsl_booke_mmu.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 1dabe1a1751b..dfd292748e6e 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -179,9 +179,14 @@ void __init
179adjust_total_lowmem(void) 179adjust_total_lowmem(void)
180{ 180{
181 phys_addr_t ram; 181 phys_addr_t ram;
182 unsigned int max_cam = 28; /* 2^28 = 256 Mb */ 182 unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
183 char buf[ARRAY_SIZE(cam) * 5 + 1], *p = buf; 183 char buf[ARRAY_SIZE(cam) * 5 + 1], *p = buf;
184 int i; 184 int i;
185 unsigned long virt = PAGE_OFFSET & 0xffffffffUL;
186 unsigned long phys = memstart_addr & 0xffffffffUL;
187
188 /* Convert (4^max) kB to (2^max) bytes */
189 max_cam = max_cam * 2 + 10;
185 190
186 /* adjust lowmem size to __max_low_memory */ 191 /* adjust lowmem size to __max_low_memory */
187 ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem); 192 ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem);
@@ -190,11 +195,18 @@ adjust_total_lowmem(void)
190 __max_low_memory = 0; 195 __max_low_memory = 0;
191 for (i = 0; ram && i < ARRAY_SIZE(cam); i++) { 196 for (i = 0; ram && i < ARRAY_SIZE(cam); i++) {
192 unsigned int camsize = __ilog2(ram) & ~1U; 197 unsigned int camsize = __ilog2(ram) & ~1U;
198 unsigned int align = __ffs(virt | phys) & ~1U;
199
200 if (camsize > align)
201 camsize = align;
193 if (camsize > max_cam) 202 if (camsize > max_cam)
194 camsize = max_cam; 203 camsize = max_cam;
204
195 cam[i] = 1UL << camsize; 205 cam[i] = 1UL << camsize;
196 ram -= cam[i]; 206 ram -= cam[i];
197 __max_low_memory += cam[i]; 207 __max_low_memory += cam[i];
208 virt += cam[i];
209 phys += cam[i];
198 210
199 p += sprintf(p, "%lu/", cam[i] >> 20); 211 p += sprintf(p, "%lu/", cam[i] >> 20);
200 } 212 }