diff options
author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2008-12-14 14:44:51 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2008-12-15 23:53:34 -0500 |
commit | f63837f0581fe580168ae1a7d178ded935411747 (patch) | |
tree | ea4956ae770193ad2d18f5be599df44014419577 /arch/powerpc/mm | |
parent | e41e811a79a4e328005be2744c3076ebde455088 (diff) |
powerpc/mm: Remove flush_HPTE()
The function flush_HPTE() is used in only one place, the implementation
of DEBUG_PAGEALLOC on ppc32.
It's actually a dup of flush_tlb_page() though it's -slightly- more
efficient on hash based processors. We remove it and replace it by
a direct call to the hash flush code on those processors and to
flush_tlb_page() for everybody else.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/mm')
-rw-r--r-- | arch/powerpc/mm/mmu_decl.h | 17 | ||||
-rw-r--r-- | arch/powerpc/mm/pgtable_32.c | 6 |
2 files changed, 5 insertions, 18 deletions
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h index fab3cfad4099..b4344fd30f2a 100644 --- a/arch/powerpc/mm/mmu_decl.h +++ b/arch/powerpc/mm/mmu_decl.h | |||
@@ -58,17 +58,14 @@ extern phys_addr_t lowmem_end_addr; | |||
58 | * architectures. -- Dan | 58 | * architectures. -- Dan |
59 | */ | 59 | */ |
60 | #if defined(CONFIG_8xx) | 60 | #if defined(CONFIG_8xx) |
61 | #define flush_HPTE(X, va, pg) _tlbie(va, 0 /* 8xx doesn't care about PID */) | ||
62 | #define MMU_init_hw() do { } while(0) | 61 | #define MMU_init_hw() do { } while(0) |
63 | #define mmu_mapin_ram() (0UL) | 62 | #define mmu_mapin_ram() (0UL) |
64 | 63 | ||
65 | #elif defined(CONFIG_4xx) | 64 | #elif defined(CONFIG_4xx) |
66 | #define flush_HPTE(pid, va, pg) _tlbie(va, pid) | ||
67 | extern void MMU_init_hw(void); | 65 | extern void MMU_init_hw(void); |
68 | extern unsigned long mmu_mapin_ram(void); | 66 | extern unsigned long mmu_mapin_ram(void); |
69 | 67 | ||
70 | #elif defined(CONFIG_FSL_BOOKE) | 68 | #elif defined(CONFIG_FSL_BOOKE) |
71 | #define flush_HPTE(pid, va, pg) _tlbie(va, pid) | ||
72 | extern void MMU_init_hw(void); | 69 | extern void MMU_init_hw(void); |
73 | extern unsigned long mmu_mapin_ram(void); | 70 | extern unsigned long mmu_mapin_ram(void); |
74 | extern void adjust_total_lowmem(void); | 71 | extern void adjust_total_lowmem(void); |
@@ -77,18 +74,4 @@ extern void adjust_total_lowmem(void); | |||
77 | /* anything 32-bit except 4xx or 8xx */ | 74 | /* anything 32-bit except 4xx or 8xx */ |
78 | extern void MMU_init_hw(void); | 75 | extern void MMU_init_hw(void); |
79 | extern unsigned long mmu_mapin_ram(void); | 76 | extern unsigned long mmu_mapin_ram(void); |
80 | |||
81 | /* Be careful....this needs to be updated if we ever encounter 603 SMPs, | ||
82 | * which includes all new 82xx processors. We need tlbie/tlbsync here | ||
83 | * in that case (I think). -- Dan. | ||
84 | */ | ||
85 | static inline void flush_HPTE(unsigned context, unsigned long va, | ||
86 | unsigned long pdval) | ||
87 | { | ||
88 | if ((Hash != 0) && | ||
89 | cpu_has_feature(CPU_FTR_HPTE_TABLE)) | ||
90 | flush_hash_pages(0, va, pdval, 1); | ||
91 | else | ||
92 | _tlbie(va); | ||
93 | } | ||
94 | #endif | 77 | #endif |
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c index c7b755cba26a..341472440137 100644 --- a/arch/powerpc/mm/pgtable_32.c +++ b/arch/powerpc/mm/pgtable_32.c | |||
@@ -342,7 +342,11 @@ static int __change_page_attr(struct page *page, pgprot_t prot) | |||
342 | return -EINVAL; | 342 | return -EINVAL; |
343 | set_pte_at(&init_mm, address, kpte, mk_pte(page, prot)); | 343 | set_pte_at(&init_mm, address, kpte, mk_pte(page, prot)); |
344 | wmb(); | 344 | wmb(); |
345 | flush_HPTE(0, address, pmd_val(*kpmd)); | 345 | #ifdef CONFIG_PPC_STD_MMU |
346 | flush_hash_pages(0, address, pmd_val(*kpmd), 1); | ||
347 | #else | ||
348 | flush_tlb_page(NULL, address); | ||
349 | #endif | ||
346 | pte_unmap(kpte); | 350 | pte_unmap(kpte); |
347 | 351 | ||
348 | return 0; | 352 | return 0; |