diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-18 09:31:43 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-18 09:31:43 -0400 |
commit | 0a95d92c0054e74fb79607ac2df958b7bf295706 (patch) | |
tree | e2c5f836e799dcfd72904949be47595af91432e7 /arch/powerpc/mm | |
parent | 08351fc6a75731226e1112fc7254542bd3a2912e (diff) | |
parent | 831532035b12a5f7b600515a6f4da0b207b82d6e (diff) |
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (62 commits)
powerpc/85xx: Fix signedness bug in cache-sram
powerpc/fsl: 85xx: document cache sram bindings
powerpc/fsl: define binding for fsl mpic interrupt controllers
powerpc/fsl_msi: Handle msi-available-ranges better
drivers/serial/ucc_uart.c: Add of_node_put to avoid memory leak
powerpc/85xx: Fix SPE float to integer conversion failure
powerpc/85xx: Update sata controller compatible for p1022ds board
ATA: Add FSL sata v2 controller support
powerpc/mpc8xxx_gpio: simplify searching for 'fsl, qoriq-gpio' compatiable
powerpc/8xx: remove obsolete mgsuvd board
powerpc/82xx: rename and update mgcoge board support
powerpc/83xx: rename and update kmeter1
powerpc/85xx: Workaroudn e500 CPU erratum A005
powerpc/fsl_pci: Add support for FSL PCIe controllers v2.x
powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e
powerpc/pseries: Disable MSI using new interface if possible
powerpc: Enable GENERIC_HARDIRQS_NO_DEPRECATED.
powerpc: core irq_data conversion.
powerpc: sysdev/xilinx_intc irq_data conversion.
powerpc: sysdev/uic irq_data conversion.
...
Fix up conflicts in arch/powerpc/sysdev/fsl_msi.c (due to getting rid of
of_platform_driver in arch/powerpc)
Diffstat (limited to 'arch/powerpc/mm')
-rw-r--r-- | arch/powerpc/mm/init_32.c | 2 | ||||
-rw-r--r-- | arch/powerpc/mm/tlb_nohash_low.S | 35 |
2 files changed, 36 insertions, 1 deletions
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c index 742da43b4ab6..d65b591e5556 100644 --- a/arch/powerpc/mm/init_32.c +++ b/arch/powerpc/mm/init_32.c | |||
@@ -148,7 +148,7 @@ void __init MMU_init(void) | |||
148 | lowmem_end_addr = memstart_addr + total_lowmem; | 148 | lowmem_end_addr = memstart_addr + total_lowmem; |
149 | #ifndef CONFIG_HIGHMEM | 149 | #ifndef CONFIG_HIGHMEM |
150 | total_memory = total_lowmem; | 150 | total_memory = total_lowmem; |
151 | memblock_enforce_memory_limit(lowmem_end_addr); | 151 | memblock_enforce_memory_limit(total_lowmem); |
152 | memblock_analyze(); | 152 | memblock_analyze(); |
153 | #endif /* CONFIG_HIGHMEM */ | 153 | #endif /* CONFIG_HIGHMEM */ |
154 | } | 154 | } |
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index af405eefe48d..7c63c0ed4f1b 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S | |||
@@ -189,6 +189,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) | |||
189 | blr | 189 | blr |
190 | 190 | ||
191 | #ifdef CONFIG_PPC_47x | 191 | #ifdef CONFIG_PPC_47x |
192 | |||
193 | /* | ||
194 | * 47x variant of icbt | ||
195 | */ | ||
196 | # define ICBT(CT,RA,RB) \ | ||
197 | .long 0x7c00002c | ((CT) << 21) | ((RA) << 16) | ((RB) << 11) | ||
198 | |||
192 | /* | 199 | /* |
193 | * _tlbivax_bcast is only on 47x. We don't bother doing a runtime | 200 | * _tlbivax_bcast is only on 47x. We don't bother doing a runtime |
194 | * check though, it will blow up soon enough if we mistakenly try | 201 | * check though, it will blow up soon enough if we mistakenly try |
@@ -206,7 +213,35 @@ _GLOBAL(_tlbivax_bcast) | |||
206 | isync | 213 | isync |
207 | eieio | 214 | eieio |
208 | tlbsync | 215 | tlbsync |
216 | BEGIN_FTR_SECTION | ||
217 | b 1f | ||
218 | END_FTR_SECTION_IFSET(CPU_FTR_476_DD2) | ||
219 | sync | ||
220 | wrtee r10 | ||
221 | blr | ||
222 | /* | ||
223 | * DD2 HW could hang if in instruction fetch happens before msync completes. | ||
224 | * Touch enough instruction cache lines to ensure cache hits | ||
225 | */ | ||
226 | 1: mflr r9 | ||
227 | bl 2f | ||
228 | 2: mflr r6 | ||
229 | li r7,32 | ||
230 | ICBT(0,r6,r7) /* touch next cache line */ | ||
231 | add r6,r6,r7 | ||
232 | ICBT(0,r6,r7) /* touch next cache line */ | ||
233 | add r6,r6,r7 | ||
234 | ICBT(0,r6,r7) /* touch next cache line */ | ||
209 | sync | 235 | sync |
236 | nop | ||
237 | nop | ||
238 | nop | ||
239 | nop | ||
240 | nop | ||
241 | nop | ||
242 | nop | ||
243 | nop | ||
244 | mtlr r9 | ||
210 | wrtee r10 | 245 | wrtee r10 |
211 | blr | 246 | blr |
212 | #endif /* CONFIG_PPC_47x */ | 247 | #endif /* CONFIG_PPC_47x */ |