powerpc/47x: Base ppc476 support

This patch adds the base support for the 476 processor.  The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.

The goal is to have a single binary that will run on 44x and 47x, but
we still have some details to work out.  The biggest is that the L1 cache
line size differs on the two platforms, but it's currently a compile-time
option.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Torez Smith  <lnxtorez@linux.vnet.ibm.com>
Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

4 files changed, 255 insertions, 22 deletions

diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 3986264b0993..d8c6efb32bc6 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -38,7 +38,9 @@ unsigned int tlb_44x_index; /* = 0 */
 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
 int icache_44x_need_flush;
 
-static void __init ppc44x_update_tlb_hwater(void)
+unsigned long tlb_47x_boltmap[1024/8];
+
+static void __cpuinit ppc44x_update_tlb_hwater(void)
 {
         extern unsigned int tlb_44x_patch_hwater_D[];
         extern unsigned int tlb_44x_patch_hwater_I[];
@@ -59,7 +61,7 @@ static void __init ppc44x_update_tlb_hwater(void)
 }
 
 /*
- * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
+ * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
  */
 static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
 {
@@ -67,12 +69,18 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
 
         ppc44x_update_tlb_hwater();
 
+        mtspr(SPRN_MMUCR, 0);
+
         __asm__ __volatile__(
                 "tlbwe  %2,%3,%4\n"
                 "tlbwe  %1,%3,%5\n"
                 "tlbwe  %0,%3,%6\n"
         :
+#ifdef CONFIG_PPC47x
+        : "r" (PPC47x_TLB2_S_RWX),
+#else
         : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
+#endif
           "r" (phys),
           "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
           "r" (entry),
@@ -81,8 +89,93 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
           "i" (PPC44x_TLB_ATTRIB));
 }
 
+static int __init ppc47x_find_free_bolted(void)
+{
+        unsigned int mmube0 = mfspr(SPRN_MMUBE0);
+        unsigned int mmube1 = mfspr(SPRN_MMUBE1);
+
+        if (!(mmube0 & MMUBE0_VBE0))
+                return 0;
+        if (!(mmube0 & MMUBE0_VBE1))
+                return 1;
+        if (!(mmube0 & MMUBE0_VBE2))
+                return 2;
+        if (!(mmube1 & MMUBE1_VBE3))
+                return 3;
+        if (!(mmube1 & MMUBE1_VBE4))
+                return 4;
+        if (!(mmube1 & MMUBE1_VBE5))
+                return 5;
+        return -1;
+}
+
+static void __init ppc47x_update_boltmap(void)
+{
+        unsigned int mmube0 = mfspr(SPRN_MMUBE0);
+        unsigned int mmube1 = mfspr(SPRN_MMUBE1);
+
+        if (mmube0 & MMUBE0_VBE0)
+                __set_bit((mmube0 >> MMUBE0_IBE0_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube0 & MMUBE0_VBE1)
+                __set_bit((mmube0 >> MMUBE0_IBE1_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube0 & MMUBE0_VBE2)
+                __set_bit((mmube0 >> MMUBE0_IBE2_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube1 & MMUBE1_VBE3)
+                __set_bit((mmube1 >> MMUBE1_IBE3_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube1 & MMUBE1_VBE4)
+                __set_bit((mmube1 >> MMUBE1_IBE4_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+        if (mmube1 & MMUBE1_VBE5)
+                __set_bit((mmube1 >> MMUBE1_IBE5_SHIFT) & 0xff,
+                          tlb_47x_boltmap);
+}
+
+/*
+ * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
+ */
+static void __cpuinit ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
+{
+        unsigned int rA;
+        int bolted;
+
+        /* Base rA is HW way select, way 0, bolted bit set */
+        rA = 0x88000000;
+
+        /* Look for a bolted entry slot */
+        bolted = ppc47x_find_free_bolted();
+        BUG_ON(bolted < 0);
+
+        /* Insert bolted slot number */
+        rA |= bolted << 24;
+
+        pr_debug("256M TLB entry for 0x%08x->0x%08x in bolt slot %d\n",
+                 virt, phys, bolted);
+
+        mtspr(SPRN_MMUCR, 0);
+
+        __asm__ __volatile__(
+                "tlbwe  %2,%3,0\n"
+                "tlbwe  %1,%3,1\n"
+                "tlbwe  %0,%3,2\n"
+                :
+                : "r" (PPC47x_TLB2_SW | PPC47x_TLB2_SR |
+                       PPC47x_TLB2_SX
+#ifdef CONFIG_SMP
+                       | PPC47x_TLB2_M
+#endif
+                       ),
+                  "r" (phys),
+                  "r" (virt | PPC47x_TLB0_VALID | PPC47x_TLB0_256M),
+                  "r" (rA));
+}
+
 void __init MMU_init_hw(void)
 {
+        /* This is not useful on 47x but won't hurt either */
         ppc44x_update_tlb_hwater();
 
         flush_instruction_cache();
@@ -95,8 +188,51 @@ unsigned long __init mmu_mapin_ram(unsigned long top)
         /* Pin in enough TLBs to cover any lowmem not covered by the
          * initial 256M mapping established in head_44x.S */
         for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
-             addr += PPC_PIN_SIZE)
-                ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
+             addr += PPC_PIN_SIZE) {
+                if (mmu_has_feature(MMU_FTR_TYPE_47x))
+                        ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
+                else
+                        ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
+        }
+        if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
+                ppc47x_update_boltmap();
 
+#ifdef DEBUG
+                {
+                        int i;
+
+                        printk(KERN_DEBUG "bolted entries: ");
+                        for (i = 0; i < 255; i++) {
+                                if (test_bit(i, tlb_47x_boltmap))
+                                        printk("%d ", i);
+                        }
+                        printk("\n");
+                }
+#endif /* DEBUG */
+        }
         return total_lowmem;
 }
+
+#ifdef CONFIG_SMP
+void __cpuinit mmu_init_secondary(int cpu)
+{
+        unsigned long addr;
+
+        /* Pin in enough TLBs to cover any lowmem not covered by the
+         * initial 256M mapping established in head_44x.S
+         *
+         * WARNING: This is called with only the first 256M of the
+         * linear mapping in the TLB and we can't take faults yet
+         * so beware of what this code uses. It runs off a temporary
+         * stack. current (r2) isn't initialized, smp_processor_id()
+         * will not work, current thread info isn't accessible, ...
+         */
+        for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
+             addr += PPC_PIN_SIZE) {
+                if (mmu_has_feature(MMU_FTR_TYPE_47x))
+                        ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
+                else
+                        ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
+        }
+}
+#endif /* CONFIG_SMP */
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index 1f2d9ff09895..ddfd7ad4e1d6 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -395,10 +395,18 @@ void __init mmu_context_init(void)
          * the PID/TID comparison is disabled, so we can use a TID of zero
          * to represent all kernel pages as shared among all contexts.
          *      -- Dan
+         *
+         * The IBM 47x core supports 16-bit PIDs, thus 65535 contexts. We
+         * should normally never have to steal though the facility is
+         * present if needed.
+         *      -- BenH
          */
         if (mmu_has_feature(MMU_FTR_TYPE_8xx)) {
                 first_context = 0;
                 last_context = 15;
+        } else if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
+                first_context = 1;
+                last_context = 65535;
         } else {
                 first_context = 1;
                 last_context = 255;
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index d49a77503e19..eb11d5d2aa94 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -69,12 +69,7 @@ static inline void _tlbil_va(unsigned long address, unsigned int pid,
 }
 #endif /* CONIFG_8xx */
 
-/*
- * As of today, we don't support tlbivax broadcast on any
- * implementation. When that becomes the case, this will be
- * an extern.
- */
-#ifdef CONFIG_PPC_BOOK3E
+#if defined(CONFIG_PPC_BOOK3E) || defined(CONFIG_PPC_47x)
 extern void _tlbivax_bcast(unsigned long address, unsigned int pid,
                            unsigned int tsize, unsigned int ind);
 #else
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index bbdc5b577b85..e925cb58afd9 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -10,7 +10,7 @@
  *      - tlbil_va
  *      - tlbil_pid
  *      - tlbil_all
- *      - tlbivax_bcast (not yet)
+ *      - tlbivax_bcast
  *
  * Code mostly moved over from misc_32.S
  *
@@ -33,6 +33,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
 #include <asm/processor.h>
+#include <asm/bug.h>
 
 #if defined(CONFIG_40x)
 
@@ -65,7 +66,7 @@ _GLOBAL(__tlbil_va)
  * Nothing to do for 8xx, everything is inline
  */
 
-#elif defined(CONFIG_44x)
+#elif defined(CONFIG_44x) /* Includes 47x */
 
 /*
  * 440 implementation uses tlbsx/we for tlbil_va and a full sweep
@@ -73,7 +74,13 @@ _GLOBAL(__tlbil_va)
  */
 _GLOBAL(__tlbil_va)
         mfspr   r5,SPRN_MMUCR
-        rlwimi  r5,r4,0,24,31                   /* Set TID */
+        mfmsr   r10
+
+        /*
+         * We write 16 bits of STID since 47x supports that much, we
+         * will never be passed out of bounds values on 440 (hopefully)
+         */
+        rlwimi  r5,r4,0,16,31
 
         /* We have to run the search with interrupts disabled, otherwise
          * an interrupt which causes a TLB miss can clobber the MMUCR
@@ -83,24 +90,41 @@ _GLOBAL(__tlbil_va)
          * and restoring MMUCR, so only normal interrupts have to be
          * taken care of.
          */
-        mfmsr   r4
         wrteei  0
         mtspr   SPRN_MMUCR,r5
-        tlbsx.  r3, 0, r3
-        wrtee   r4
-        bne     1f
+        tlbsx.  r6,0,r3
+        bne     10f
         sync
-        /* There are only 64 TLB entries, so r3 < 64,
-         * which means bit 22, is clear.  Since 22 is
-         * the V bit in the TLB_PAGEID, loading this
+BEGIN_MMU_FTR_SECTION
+        b       2f
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
+        /* On 440 There are only 64 TLB entries, so r3 < 64, which means bit
+         * 22, is clear.  Since 22 is the V bit in the TLB_PAGEID, loading this
          * value will invalidate the TLB entry.
          */
-        tlbwe   r3, r3, PPC44x_TLB_PAGEID
+        tlbwe   r6,r6,PPC44x_TLB_PAGEID
         isync
-1:      blr
+10:     wrtee   r10
+        blr
+2:
+#ifdef CONFIG_PPC_47x
+        oris    r7,r6,0x8000    /* specify way explicitely */
+        clrrwi  r4,r3,12        /* get an EPN for the hashing with V = 0 */
+        ori     r4,r4,PPC47x_TLBE_SIZE
+        tlbwe   r4,r7,0         /* write it */
+        isync
+        wrtee   r10
+        blr
+#else /* CONFIG_PPC_47x */
+1:      trap
+        EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
+#endif /* !CONFIG_PPC_47x */
 
 _GLOBAL(_tlbil_all)
 _GLOBAL(_tlbil_pid)
+BEGIN_MMU_FTR_SECTION
+        b       2f
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
         li      r3,0
         sync
 
@@ -115,6 +139,76 @@ _GLOBAL(_tlbil_pid)
 
         isync
         blr
+2:
+#ifdef CONFIG_PPC_47x
+        /* 476 variant. There's not simple way to do this, hopefully we'll
+         * try to limit the amount of such full invalidates
+         */
+        mfmsr   r11             /* Interrupts off */
+        wrteei  0
+        li      r3,-1           /* Current set */
+        lis     r10,tlb_47x_boltmap@h
+        ori     r10,r10,tlb_47x_boltmap@l
+        lis     r7,0x8000       /* Specify way explicitely */
+
+        b       9f              /* For each set */
+
+1:      li      r9,4            /* Number of ways */
+        li      r4,0            /* Current way */
+        li      r6,0            /* Default entry value 0 */
+        andi.   r0,r8,1         /* Check if way 0 is bolted */
+        mtctr   r9              /* Load way counter */
+        bne-    3f              /* Bolted, skip loading it */
+
+2:      /* For each way */
+        or      r5,r3,r4        /* Make way|index for tlbre */
+        rlwimi  r5,r5,16,8,15   /* Copy index into position */
+        tlbre   r6,r5,0         /* Read entry */
+3:      addis   r4,r4,0x2000    /* Next way */
+        andi.   r0,r6,PPC47x_TLB0_VALID /* Valid entry ? */
+        beq     4f              /* Nope, skip it */
+        rlwimi  r7,r5,0,1,2     /* Insert way number */
+        rlwinm  r6,r6,0,21,19   /* Clear V */
+        tlbwe   r6,r7,0         /* Write it */
+4:      bdnz    2b              /* Loop for each way */
+        srwi    r8,r8,1         /* Next boltmap bit */
+9:      cmpwi   cr1,r3,255      /* Last set done ? */
+        addi    r3,r3,1         /* Next set */
+        beq     cr1,1f          /* End of loop */
+        andi.   r0,r3,0x1f      /* Need to load a new boltmap word ? */
+        bne     1b              /* No, loop */
+        lwz     r8,0(r10)       /* Load boltmap entry */
+        addi    r10,r10,4       /* Next word */
+        b       1b              /* Then loop */
+1:      isync                   /* Sync shadows */
+        wrtee   r11
+#else /* CONFIG_PPC_47x */
+1:      trap
+        EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
+#endif /* !CONFIG_PPC_47x */
+        blr
+
+#ifdef CONFIG_PPC_47x
+/*
+ * _tlbivax_bcast is only on 47x. We don't bother doing a runtime
+ * check though, it will blow up soon enough if we mistakenly try
+ * to use it on a 440.
+ */
+_GLOBAL(_tlbivax_bcast)
+        mfspr   r5,SPRN_MMUCR
+        mfmsr   r10
+        rlwimi  r5,r4,0,16,31
+        wrteei  0
+        mtspr   SPRN_MMUCR,r5
+/*      tlbivax 0,r3 - use .long to avoid binutils deps */
+        .long 0x7c000624 | (r3 << 11)
+        isync
+        eieio
+        tlbsync
+        sync
+        wrtee   r10
+        blr
+#endif /* CONFIG_PPC_47x */
 
 #elif defined(CONFIG_FSL_BOOKE)
 /*