powerpc: Enforce usage of RA 0-R31 where possible

Some macros use RA where when RA=R0 the values is 0, so make this
the enforced mnemonic in the macro.

Idea suggested by Andreas Schwab.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2 files changed, 13 insertions, 13 deletions

diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index 4b9e2643d21b..f09d48e3268d 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -126,7 +126,7 @@ BEGIN_MMU_FTR_SECTION
         /* Set the TLB reservation and search for existing entry. Then load
          * the entry.
          */
-        PPC_TLBSRX_DOT(R0,R16)
+        PPC_TLBSRX_DOT(0,R16)
         ldx     r14,r14,r15             /* grab pgd entry */
         beq     normal_tlb_miss_done    /* tlb exists already, bail */
 MMU_FTR_SECTION_ELSE
@@ -395,7 +395,7 @@ BEGIN_MMU_FTR_SECTION
         /* Set the TLB reservation and search for existing entry. Then load
          * the entry.
          */
-        PPC_TLBSRX_DOT(R0,R16)
+        PPC_TLBSRX_DOT(0,R16)
         ld      r14,0(r10)
         beq     normal_tlb_miss_done
 MMU_FTR_SECTION_ELSE
@@ -528,7 +528,7 @@ BEGIN_MMU_FTR_SECTION
         /* Search if we already have a TLB entry for that virtual address, and
          * if we do, bail out.
          */
-        PPC_TLBSRX_DOT(R0,R16)
+        PPC_TLBSRX_DOT(0,R16)
         beq     virt_page_table_tlb_miss_done
 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
 
@@ -779,7 +779,7 @@ htw_tlb_miss:
          *
          * MAS1:IND should be already set based on MAS4
          */
-        PPC_TLBSRX_DOT(R0,R16)
+        PPC_TLBSRX_DOT(0,R16)
         beq     htw_tlb_miss_done
 
         /* Now, we need to walk the page tables. First check if we are in
@@ -919,7 +919,7 @@ tlb_load_linear:
         mtspr   SPRN_MAS1,r15
 
         /* Already somebody there ? */
-        PPC_TLBSRX_DOT(R0,R16)
+        PPC_TLBSRX_DOT(0,R16)
         beq     tlb_load_linear_done
 
         /* Now we build the remaining MAS. MAS0 and 2 should be fine
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 75a9d14a3dea..fab919fd1384 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -266,7 +266,7 @@ BEGIN_MMU_FTR_SECTION
         andi.   r3,r3,MMUCSR0_TLBFI@l
         bne     1b
 MMU_FTR_SECTION_ELSE
-        PPC_TLBILX_ALL(R0,R0)
+        PPC_TLBILX_ALL(0,R0)
 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
         msync
         isync
@@ -279,7 +279,7 @@ BEGIN_MMU_FTR_SECTION
         wrteei  0
         mfspr   r4,SPRN_MAS6    /* save MAS6 */
         mtspr   SPRN_MAS6,r3
-        PPC_TLBILX_PID(R0,R0)
+        PPC_TLBILX_PID(0,R0)
         mtspr   SPRN_MAS6,r4    /* restore MAS6 */
         wrtee   r10
 MMU_FTR_SECTION_ELSE
@@ -313,7 +313,7 @@ BEGIN_MMU_FTR_SECTION
         mtspr   SPRN_MAS1,r4
         tlbwe
 MMU_FTR_SECTION_ELSE
-        PPC_TLBILX_VA(R0,R3)
+        PPC_TLBILX_VA(0,R3)
 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
         msync
         isync
@@ -331,7 +331,7 @@ _GLOBAL(_tlbil_pid)
         mfmsr   r10
         wrteei  0
         mtspr   SPRN_MAS6,r4
-        PPC_TLBILX_PID(R0,R0)
+        PPC_TLBILX_PID(0,R0)
         wrtee   r10
         msync
         isync
@@ -343,14 +343,14 @@ _GLOBAL(_tlbil_pid_noind)
         ori     r4,r4,MAS6_SIND
         wrteei  0
         mtspr   SPRN_MAS6,r4
-        PPC_TLBILX_PID(R0,R0)
+        PPC_TLBILX_PID(0,R0)
         wrtee   r10
         msync
         isync
         blr
 
 _GLOBAL(_tlbil_all)
-        PPC_TLBILX_ALL(R0,R0)
+        PPC_TLBILX_ALL(0,R0)
         msync
         isync
         blr
@@ -364,7 +364,7 @@ _GLOBAL(_tlbil_va)
         beq     1f
         rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
 1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
-        PPC_TLBILX_VA(R0,R3)
+        PPC_TLBILX_VA(0,R3)
         msync
         isync
         wrtee   r10
@@ -379,7 +379,7 @@ _GLOBAL(_tlbivax_bcast)
         beq     1f
         rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
 1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
-        PPC_TLBIVAX(R0,R3)
+        PPC_TLBIVAX(0,R3)
         eieio
         tlbsync
         sync