diff options
| author | Matt Evans <matt@ozlabs.org> | 2011-04-06 15:48:50 -0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2011-04-27 00:18:52 -0400 |
| commit | 44ae3ab3358e962039c36ad4ae461ae9fb29596c (patch) | |
| tree | 08c0628a5226c0535b7fe236be64b48e5eb0fbd6 /arch/powerpc/mm/hash_low_64.S | |
| parent | eca590f402332ab873d13f2d8d00fa0b91cfff36 (diff) | |
powerpc: Free up some CPU feature bits by moving out MMU-related features
Some of the 64bit PPC CPU features are MMU-related, so this patch moves
them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to
mmu_has_feature(), and seven feature bits are freed as a result.
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm/hash_low_64.S')
| -rw-r--r-- | arch/powerpc/mm/hash_low_64.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S index 5b7dd4ea02b5..a242b5d7cbe4 100644 --- a/arch/powerpc/mm/hash_low_64.S +++ b/arch/powerpc/mm/hash_low_64.S | |||
| @@ -118,7 +118,7 @@ _GLOBAL(__hash_page_4K) | |||
| 118 | BEGIN_FTR_SECTION | 118 | BEGIN_FTR_SECTION |
| 119 | cmpdi r9,0 /* check segment size */ | 119 | cmpdi r9,0 /* check segment size */ |
| 120 | bne 3f | 120 | bne 3f |
| 121 | END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) | 121 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) |
| 122 | /* Calc va and put it in r29 */ | 122 | /* Calc va and put it in r29 */ |
| 123 | rldicr r29,r5,28,63-28 | 123 | rldicr r29,r5,28,63-28 |
| 124 | rldicl r3,r3,0,36 | 124 | rldicl r3,r3,0,36 |
| @@ -401,7 +401,7 @@ _GLOBAL(__hash_page_4K) | |||
| 401 | BEGIN_FTR_SECTION | 401 | BEGIN_FTR_SECTION |
| 402 | cmpdi r9,0 /* check segment size */ | 402 | cmpdi r9,0 /* check segment size */ |
| 403 | bne 3f | 403 | bne 3f |
| 404 | END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) | 404 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) |
| 405 | /* Calc va and put it in r29 */ | 405 | /* Calc va and put it in r29 */ |
| 406 | rldicr r29,r5,28,63-28 /* r29 = (vsid << 28) */ | 406 | rldicr r29,r5,28,63-28 /* r29 = (vsid << 28) */ |
| 407 | rldicl r3,r3,0,36 /* r3 = (ea & 0x0fffffff) */ | 407 | rldicl r3,r3,0,36 /* r3 = (ea & 0x0fffffff) */ |
| @@ -715,7 +715,7 @@ BEGIN_FTR_SECTION | |||
| 715 | andi. r0,r31,_PAGE_NO_CACHE | 715 | andi. r0,r31,_PAGE_NO_CACHE |
| 716 | /* If so, bail out and refault as a 4k page */ | 716 | /* If so, bail out and refault as a 4k page */ |
| 717 | bne- ht64_bail_ok | 717 | bne- ht64_bail_ok |
| 718 | END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE) | 718 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_CI_LARGE_PAGE) |
| 719 | /* Prepare new PTE value (turn access RW into DIRTY, then | 719 | /* Prepare new PTE value (turn access RW into DIRTY, then |
| 720 | * add BUSY and ACCESSED) | 720 | * add BUSY and ACCESSED) |
| 721 | */ | 721 | */ |
| @@ -736,7 +736,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE) | |||
| 736 | BEGIN_FTR_SECTION | 736 | BEGIN_FTR_SECTION |
| 737 | cmpdi r9,0 /* check segment size */ | 737 | cmpdi r9,0 /* check segment size */ |
| 738 | bne 3f | 738 | bne 3f |
| 739 | END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT) | 739 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) |
| 740 | /* Calc va and put it in r29 */ | 740 | /* Calc va and put it in r29 */ |
| 741 | rldicr r29,r5,28,63-28 | 741 | rldicr r29,r5,28,63-28 |
| 742 | rldicl r3,r3,0,36 | 742 | rldicl r3,r3,0,36 |