powerpc/math-emu: Fix load/store indexed emulation

Load/store indexed instructions where the index register RA=R0, such
as "lfdx f1,0,r3", are not illegal.

Load/store indexed with update instructions where the index register
RA=R0, such as "lfdux f1,0,r3", are invalid, and, to be consistent
with existing math-emu behavior for other invalid instruction forms,
will signal as illegal.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 5 insertions, 10 deletions

diff --git a/arch/powerpc/math-emu/math.c b/arch/powerpc/math-emu/math.c
index bc901623d8df..ab151f040502 100644
--- a/arch/powerpc/math-emu/math.c
+++ b/arch/powerpc/math-emu/math.c
@@ -380,21 +380,16 @@ do_mathemu(struct pt_regs *regs)
         case XE:
                 idx = (insn >> 16) & 0x1f;
                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
-                if (!idx) {
-                        if (((insn >> 1) & 0x3ff) == STFIWX)
-                                op1 = (void *)(regs->gpr[(insn >> 11) & 0x1f]);
-                        else
-                                goto illegal;
-                } else {
-                        op1 = (void *)(regs->gpr[idx] + regs->gpr[(insn >> 11) & 0x1f]);
-                }
-
+                op1 = (void *)((idx ? regs->gpr[idx] : 0)
+                                + regs->gpr[(insn >> 11) & 0x1f]);
                 break;
 
         case XEU:
                 idx = (insn >> 16) & 0x1f;
+                if (!idx)
+                        goto illegal;
                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
-                op1 = (void *)((idx ? regs->gpr[idx] : 0)
+                op1 = (void *)(regs->gpr[idx]
                                 + regs->gpr[(insn >> 11) & 0x1f]);
                 break;